摘要
在同步(synchronous)電路中，時鐘樹因為切換頻率(frequency)高，且驅動較大的負載，所以經常是動態功率(dynamic power)消耗最主要的部分。事實上，並不一定所有的電路在同一時間點都需要運作。如果能在適當的時間，將時鐘訊號以一個控制閘關閉，使得某些不需要運作的電路“閒置(idle)”，則必定能減少整個電路的功率消耗。 本論文提出了在時鐘樹上插入clock gates 以降低時鐘樹的功率消耗，並保持零時序差異(zero skew)的演算法。我們提出的方法為，首先對合成過後電路上的flip-flops依據各自的activity patterns來分成數個群組。在電路擺置(placement)過後，再根據所有clock gates的activity patterns找出能降低功率消耗的合併或搬動的組合，並且以DME演算法將整個時鐘樹繞線完成。實驗結果顯示，我們提出的演算法所產生的時鐘樹，不僅比沒有插入clock gates的時鐘樹平均降低將近40%的功率消耗，也比只插入clock gates但沒有做最佳化的時鐘樹功率消耗減少了12%左右，並且仍為zero skew。
並列摘要
In synchronous circuit, the clock tree always become the main part of the dynamic power consumption because it switches at high frequency and drives a large capacitance. In fact, not all parts of circuit need working at the same time. The whole power consumption of the circuit can be reduced if we turn off the clock signal of the parts of the circuit which should be “idle” at appropriate time by a controllable gate. In this paper, we present a methodology not only reducing the dynamic power consumption of the clock tree by inserting clock gates but also maintaining zero-skew. The proposed method is presented as follow. First, we partition the flip-flops in the synthesized circuit to some groups according to their activity patterns. After cells placed, we want to find the combinations of flip-flops which may reduce power by the method of merging or moving according to the activity patterns of the flip-flops. The DME algorithm is used to route the clock tree. Experimental results show that the clock tree generated by our algorithm in average has 40% of power saving over the tree without inserting clock gates, and also 12% of power saving when it is compared to the gated clock tree without doing optimization.