數位化類比波形記錄器之非線性誤差消除電路

The Non-linearity Error Cancellation of Digitize Analog Waveform Recorder

范可立(Kee-Lih Fann)

指導教授 ： 鍾文耀

中原大學/工學院/電子工程研究所/碩士(2004年)

https://doi.org/10.6840/cycu200400732

摘要

目前的數位化類比波形記錄器中需要使用到中高速的類比-數位轉換器(ADC)，以便擔任高解析度、高線性度的類比到數位轉換工作。也同樣需要速度適當的數位-類比轉換器(DAC)還原類比訊號。
但是各種ADC或DAC的操作轉換時，一定都會有轉換非線性（Non-linearity, NL）發生，而這些非線性誤差參數將會大幅的影響對類比訊號的還原與解讀。傳統使用數位預設非線性模型補償方法，但需要預先校正該非線性模型，因此會消耗微控器運算與記憶體資源，而且還涉及軟體或韌體的撰寫。
本文主題就是要設計一個晶片化電路以消除上述的非線性誤差，低失真還原類比訊號。即利用SA(也有稱為SAR) ADC 的特性，將ADC與DAC的量化曲線以同一組電路完成，在DAC還原訊號階段時，即進行自我的非線性校正，故能消除波形記錄器中，主要由量化陣列所引起的量化曲線非線性問題。不但節省資源同時也更正確且能提升整體的運作效率。
同時，在本晶片的構思設計期間，學生還發現各種不同形式的ADC (例﹕SA、Flash、TIQ、Pipeline、Two stages、Delta modulation等)，都能以增加一些子電路的方式，達到將一個ADC電路功能轉換成ADC/DAC複合式(ADC/DAC Combo)電路功能的設計。雖然這些延伸的研究尚未經過實體驗證，但在概念上都是具有可能性的。

關鍵字

非線性 ； 複合式

並列摘要

Today’s Digitize Analog Waveform Recorders need medium to high speed ADC for the high resolution, high linearity analog to digital conversion. It also needs the correspondent DAC to reconstruct the analog signal.

But every ADC or DAC conversion will induce the non-linearity parameters. These parameters will infect the reconstruct and analysis of the analog signal. Normally use mathematical modeling as a correction, but it needs many Micro Processor and memory resources for modeling and calibration.

The goal is to design a chip for cancel the non-linearity. This thesis uses the characteristics of SA (also called SAR) ADC, let the two quantitative curves identical, therefore the non-linearity effect in waveform recorders can be cancelled, which is caused by quantitative curve. Which use the lower resources and perform the higher total performance.

During the development of this chip, I found that every ADC (for example: SA、Flash、TIQ、Pipeline、Two stages、Delta modulation…etc) can converse the ADC function block to a ADC/DAC combo function block by adding some fiddling circuits. Although they are not proved by chip yet but the concept has been considered.

並列關鍵字

NL ； Combo ； Non-linearity

參考文獻

[1] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford University Press, Chap. 7 and 10, 1987

[2] James L. McCreary and Paul R. Grey, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part I”, IEEE Journal of Solid State Circuit, Vol. SC-10, No. 6, pp. 371-379, December 1975

[3] Ricardo E. Suarez, Paul R. Gray, and David A. Hodges, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part II”, IEEE Journal of Solid State Circuit, Vol. SC-10, No. 6, pp. 379-385, December 1975

[7] Analysis and design of analog integrated circuits, 4e, by Gray et al, Wiley 2001

[8] Design of analog CMOS integrated circuits, by Razavi, McGraw Hill 2001