設計一顆MIPS R2000處理器並以ARM Integrator為基礎發展其軟硬體共同驗證流程

Design a MIPS R2000 Processor and Its HW/SW Co-verification Flow Base on ARM Integrator

陳侑谷(Yu-Ku Chen)

指導教授 ： 朱守禮

中原大學/工學院/資訊工程研究所/碩士(2007年)

https://doi.org/10.6840/cycu200700025

摘要

現今的電腦系統中，處理器扮演著不可或缺的角色。近十年來處理器以飛快的腳步在進步，不論在速度上或是功能上都不斷的在成長，應用層面也越來越廣泛，舉凡電腦、家電、手機及車用電子系統等等，生活上所需之電子產品幾乎都存在著處理器。在本論文中，我們將設計一顆五階管線MIPS R2000處理器，並針對管線中會發生的三大危障(hazard)：結構危障(structure hazard)、資料危障(data hazard)、控制危障(control hazard)，設計解決的機制，以增加處理器效能。

在處理器驗證方面，一般硬體設計大都只靠硬體描述語言模擬軟體來確認其功能正確性，鮮少以實際硬體從事完整系統的驗證。這樣一來，所設計的處理器並不能保證在真實硬體系統上能正確的運作。因此本論文發展一套硬體驗證環境，以驗證MIPS R2000處理器之功能正確性與實用性。在處理器發展初期，我們以ModelSim和Debussy這兩套軟體來設計並模擬驗證其功能的正確性。接著，我們將處理器整合進ARM Integrator中，並發展一套軟硬體共同驗證流程來驗證所設計之處理器，並確定MIPS R2000處理器在真實的硬體系統中也能正確無誤的執行。

最後我們將所設計之MIPS R2000處理器，透過Synopsys Design Compiler從事邏輯合成，分別以TSMC 0.13μm和UMC 0.18μm兩種不同製程之Cell Library進行合成並比較其結果，並證實本處理器在TSMC 0.13μm的製程下，其工作頻率可達148.8MHz，且晶片面積僅佔511402.8μm2。最後亦提供在Synopsys Astro中產生之晶片Layout圖。

關鍵字：MIPS R2000, ARM Integrator, 軟硬體共同驗證, von Neumann架構, Harvard 架構

關鍵字

MIPS R2000 ； Harvard 架構 ； von Neumann架構 ； 軟硬體共同驗證 ； ARM Integrator

並列摘要

Continuous growing of technology makes the head of the computer system, processor, more powerful and fast in this decade. The usage of the processors is more widely, such as desktop computer, household appliances, mobile phone, and etc… In this thesis, we design a five-stages pipelined processor based on MIPS R2000 integer instruction set. In order to improve performance, we make much effort dealing with three major hazard problems: structure hazard, data hazard, and control hazard and develop several mechanisms.

The verification is also important in processor design. More functional verifications of a hardware design are base on HDL simulator, but less on targeting on hardware to verify system integrity. Then the designed processor cannot work correctly while integrating in the real computer system. Therefore in this thesis, we develop a hardware verification platform to verify the functionality and practicability of our design MIPS R2000. In the early stage of processor design, we adopt Modelsim and Debussy to develop and simulate our processor. Then we integrate our processor into ARM Integrator and propose a HW/SW co-verification flow to verify our MIPS R2000 that can work correctly in real hardware system.

Finally we adopt Synopsys Design Compiler to synthesize our MIPS R2000 by two cell libraries, TSMC 0.13μm technology and UMC 0.18μm technology and compare their difference. The results prove the work frequency of our processor can achieve 148.8MHz targeted on 0.13μm technology. The chip area is only 511402.8μm2. The chip layout generated by Synopsys Astro is also provided.

Keywords: MIPS R2000, ARM Integrator, HW/SW co-verification, von Neumann architecture, Harvard architecture.

並列關鍵字

HW/SW co-verification ； ARM Integrator ； Harvard architecture ； von Neumann architecture ； MIPS R2000

參考文獻

[9] 江繼堯, “針對RISC電腦系統的記憶體子系統之設計”, 中原大學資訊工程所碩士論文, 2007.

[1] David A. Patterson and John L. Hennessy, “Computer Architecture A Quantitative Approach”, 3nd Edition, Morgan Kaufmann.

[3] 賴建邦, “有限狀態機為基礎之MIPS32指令集架構處理器設計”, 中原大學資訊工程所碩士論文, 2007.

[11] Gerry Kane, “MIPS RISC Architecture”, Prentice-Hall, Inc.

參考文獻