透過您的圖書館登入
IP:3.145.101.192
  • 學位論文

設計一個針對多核心系統之互聯網路的高度可擴充機制

Design A Highly Scalable Mechanism for The Interconnection Network of the Multi-core System

指導教授 : 朱守禮
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


藉由互聯網路(Interconnection Network,IN)架構來改善整體系統效能,將成為未來多核心電腦中關鍵的一環。其中Crossbar為互聯網路的主要架構之一。然而,在核心數大於16的多核心系統中,Crossbar會因為其擴充性及硬體成本而不再適用。故在這篇論文中,我們基於OpenSPARC 的環境提出了一個互聯機制的可行性研究。為了實現這個目標,我們的研究歷經以下兩個階段:首先,為了改寫OpenSPARC T1的互聯網路架構,我們針對其原始碼進行深入的探討。至於第二階段的部份,則採用OpenSPARC T1原有的迴歸(Regression)環境來驗證我們所提出的互聯機制。實驗結果顯示,我們針對多核心系統所提出的互聯機制確實是可行且成功的。

並列摘要


Improving the whole system performance by Interconnection Network (IN) architecture plays the critical role in many future multi-core computers. Crossbar is one of the principal architectures of IN. However, the crossbar will be not applicable due to its scalability and hardware cost in a multi-core (>16) system. In this paper we present a feasibility study of interconnection mechanism based on the OpenSPARC environment. Towards this purpose, the study goes through two phases. First, we conduct a detailed study of the OpenSPARC source code in order to rewrite its IN architecture. Second, we adopt the original regression environment of the OpenSPARC to verify our proposed interconnection mechanism. The experimental results show our mechanism is feasible and successful for multi-core systems.

參考文獻


[2]. Rudack, M., M. Redeker, et al. “A large-area integrated multiprocessor system for video applications”, IEEE Design & Test of Computers 19(1), pp. 6-17, 2002.
[4]. Dutta, S., R. Jensen, et al. “Viper: A multiprocessor SOC for advanced set-top box and digital TV systems”, IEEE Design & Test of Computers 18(5), pp. 21-31, 2001.
[5]. Ackland, B., A. Anesko, et al. “A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP”, Solid-State Circuits, IEEE Journal of 35(3), pp. 412-424, 2000.
[6]. J. Chaoui. “OMAP: Enabling Multimedia Applications in Third Generation Wireless Terminals”, Dedicated Systems Magazine Q2, pp. 34-39, 2001.
參考文獻

延伸閱讀