- 學位論文
針對多媒體系統晶片設計高效能記憶體子系統 與其新排程機制
Design a High-Performance Memory Subsystem with Novel Scheduling Mechanisms for a Multimedia SoC System
摘要
在消費型電子產品的蓬勃發展下，為了提供消費者更多的影音視訊整合服務，在 單一晶片內整合多個多媒體運算核心的晶片設計越來越多，但這些多媒體系統晶片的 效能，往往因為記憶體子系統的頻寬不足，而無法充分發揮。因此，本論文發展一個 新式記憶體控制器雛形，稱為“Smart Memory Controller＂，以解決記憶體子系統的效 能瓶頸。此控制器不同於傳統的記憶體控制器，能提供SOC晶片內各個核心獨立的緩 衝記憶體與頻寬，並能針對不同的應用環境，改變其設定。而本論文的重點主要為： 在此一記憶體控制器內，設計新式排程機制，以提供資料轉送與流量控制的功能，以 充分發揮記憶體的頻寬。 排程機制在記憶體控制器內扮演相當重要的角色，對於每個對記憶體發出需求的 設備，應該要如何對這些設備排序，才可以使這些設備對記憶體之間的傳輸順暢不會 有延遲的現象發生，並且可以讓記憶體的頻寬做最有效的利用。 本研究分數個階段進行：第一階段，先以SystemC語言，建立AMBA-Based SOC 基本平台，以呈現傳統多媒體系統晶片之工作負載環境，並作為新的記憶體控制器研 發之發展基礎與比較環境。第二階段，針對前述之可重組記憶體控制系統之功能，發 展適當的演算法。並在前述之模擬環境進行效能分析。第三階段，將上述之新式記憶 體控制器雛形，以SystemC設計後並在整合於業界主流的ESL塑模系統：CoWare，以 軟硬體協同模擬的方式，搭配ARM926EJS CPU Model, AMBA Bus Functional Model與 相關週邊Model，實現出適用於本記憶體控制器之SOC環境，以驗證本控制器的功能正 確性與效能增益，並針對本Smart Memory Controller之功能，設計其基本排程機制。 在廣泛驗證與效能評估後，我們發現，公平的排程機制會造成頻寬的浪費，進而 造成高頻寬需求之設備發生頻寬不足的狀況，因此，在第四階段，我們重新設計排程 機制，使其能隨頻寬需求動態調整相關之傳輸通道之參數，以能滿足所有接在Smart Memory Controller之設備，所需之頻寬需求。經過充分的實驗後，我們發現：本論文 所設計之新式排程機制確實能提供Smart Memory Controller更高的記憶體存取效能，並 能為未來的多媒體設備，所需之高頻寬記憶體存取需求，提供一可行的控制器雛形。
並列摘要
Since the continuously growing of multimedia functionalities in modern portable consuming electronics, the computer systems have to integrate multiple media processors on single chip/system to provide more capabilities. However, the insufficient bandwidth of the memory subsystem will make the performance of the multimedia modules unsatisfied. In this paper, we propose an innovative architecture of memory subsystem, called “Smart Memory Controller”, aiming for extracting more potential bandwidth of memory access to fulfill the requirements of multiple multimedia processors dynamically. Different from the traditional memory controller, this controller can offer an individual buffer and bandwidth for each attached IP. The main objective of this study is designing a novel scheduling mechanism for the innovative architecture of memory subsystem which can provide enough bandwidth for high memory bandwidth multimedia processors in the modern SOC chip. The proposed hardware scheduling mechanisms are quite important in our Smart Memory Controller architecture. Integrated with several reconfigurable buffers and interconnection devices, this memory subsystem can provide the lossless quality even when it attached two high definition MPEG4 encoders and two MPEG4 decoders. There are several stages to accomplish the research: In the first stage, we set up the AMBA-Based SOC basic platform by SystemC HDL, to present the basic environment of the traditional multimedia SOC system, and also provide a comparative environment for the new memory controller. The second stage, aim at the mentioned new memory subsystem, we develop the proper algorithms. At the third stage, the novel memory controller model has been implemented by SystemC HDL. And then, we combine this model and the relevant peripheral models to the ESL modeling system: CoWare. The functional verification and performance evaluation of the whole system have been examined. Then we design the scheduling mechanism, in accordance with the function of the Smart Memory Controller. After comprehensively exemption of more configurations of attached IPs, we find that the fair scheduling mechanisms will waste the bandwidth and make the high-bandwidth requirement device starvation. Therefore, in the fourth stage, we redesign the scheduling mechanisms which can adjust the parameters and bandwidth requirements of the relevant transmission channels dynamically to fulfill the requirements of the attached IPs. After adequately experiment, we find that the proposed novel scheduling mechanisms can make Smart Memory Controller higher memory access performance, and can provide one feasible memory controller model for the future multimedia equipments which need the high-bandwidth memory access capabilities.