應用於環景顯示系統之特徵點檢測晶片設計

Feature Point Detection Chip Design for Surrounding View System

溫馥榕(Fu-Jung Wen)

指導教授 ： 陳世綸 ； 邱奕世

中原大學/電機資訊學院/電子工程研究所/碩士(2020年)

https://doi.org/10.6840/cycu202000731

摘要

本論文提出以硬體為導向之應用於環景系統的影像拼接演算法，並以積體電路實現特徵點檢測設計。現今的影像拼接演算法往往為了獲取高品質的拼接結果，導致演算法的複雜度提高而無法達到即時性的需求。因此，以低複雜度和高品質為設計目標，提出之影像拼接演算法包含五大部分：特徵點檢測、描述符建構、特徵點匹配、影像校正及影像融合技術。為使整體設計的運行速度提升，以跨列檢索及改進之FAST演算法降低特徵檢測的耗時。在運算量較大的描述符建構階段，提出基於區塊之進階篩選方法，降低整體設計的計算量。另外，採用化簡之最佳接縫搜索演算法，以同時達到降低複雜度與保持拼接影像品質的目的。與先前的相關研究文獻相比，本論文提出之影像拼接演算法具有較低的複雜度及高精準度的特性。此外，在拼接結果中，更能獲得和現有的商業軟體相近的高品質拼接影像。
在硬體方面，本論文以位移器和加法器取代浮點數運算，並以二值化處理與布林運算取代演算法中最耗時的重複運算部分。此外，以線緩衝記憶體暫存待檢測像素及特徵強度值，使特徵檢測電路及非極大值抑制電路不致遺失所需之資訊，而導致後續產生誤差。整體設計皆以管線化架構並行處理，大幅地提升對於高解析度影像的兼容性。藉由提出之積體電路架構，可使得整體設計在維持影像品質的同時兼具實時性。本論文提出之特徵檢測設計採用台積電0.18-μm CMOS製程實現，晶片面積為183,569 μm2，其中包含23,852個邏輯閘，操作頻率可達到140 MHz，其功率消耗為10.01 mW。相較於目前的電路設計，本論文提出之電路架構可有效地降低約 9% 之邏輯閘數，具有更低的硬體成本及高精確度的特徵檢測結果。

關鍵字

特徵點 ； FAST演算法 ； 影像拼接 ； 環景顯示 ； 晶片設計

並列摘要

This thesis proposes a hardware-oriented image stitching algorithm for the surrounding view system. Today's image stitching algorithms are often in pursuit of high-quality stitching results, resulting in the high complexity of the algorithm and unavailable in real-time. The proposed algorithm is designed with low complexity and high quality, including feature point detection, descriptor construction, feature matching, image alignment, and image fusion. An improved FAST algorithm, a block-based screening method, and a simplified optimal seam algorithm are proposed in this thesis. Compared with other studies, this thesis can obtain high-quality stitching results with lower complexity and high accuracy, and even have similar performance with the commercial software.
In hardware, this thesis replaces floating-point arithmetic and the time-consuming repeated calculations parts with shifters, adders, binarization, and Boolean operations. Moreover, storing detected pixels and feature intensity with the line buffer to ensure that no errors caused due to the loss of required information. The design also adopts pipeline architecture, which significantly improves the compatibility with high-resolution images. The proposed feature detection design uses TSMC 0.18-μm CMOS process with a chip area of 183,569 μm2 and contains 23,852 gate counts. The chip operating frequency can reach 140 MHz, and the power consumption is 10.2 mW. Compared with the existing design, the circuit architecture proposed in this thesis effectively reduces the gate counts by 9%, with lower cost and high-quality image stitching performance.

並列關鍵字

Feature Point ； FAST Algorithm ； Image Stitching ； Surrounding View ； Chip Design

參考文獻

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