數位類比轉換器之設計與分析

Design and Analysis of Digital to Analog Converter

邱柏翰(Bo-Han Chiu)

指導教授 ： 陳淳杰

中原大學/電機資訊學院/電子工程研究所/碩士(2017年)

https://doi.org/10.6840/cycu201700579

摘要

本篇論文設計一個六位元每秒十億次取樣頻率的摺疊R-2R階梯電流導引式數位類比轉換器。設計平台使用的是TSMC 0.18μm 1P6M CMOS製程。電源供應為1.8V情況下，模擬結果功率消耗為1.93mW，DNL為 ± 0.08LSB，INL為 ± 0.04LSB。取樣頻率為1GHz輸入頻率為230MHz的情況下可以得到ENOB值為5.81bit，SFDR為50.17dB。

關鍵字

數位類比轉換器 ； R-2R

並列摘要

In this paper, a 6-bit 1 GS/s folded R-2R ladder-based current-steering Digital-to-Analog Converter is designed. Design platform is TSMC 0.18μm 1P6M CMOS process. At 1.8 power supply, the power consumption simulation results is 1.93mW. The DNL is ±0.08LSB, the INL is ±0.04LSB. With sampling frequency at 1GHz and input frequency of 230MHz, the ENOB is 5.81bits, SFDR is 50.17dB.

並列關鍵字

digital-to-analog converter ； R-2R

參考文獻

[11]楊皓翔, “一個六位元每秒二十億次取樣頻率的虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器”,中原大學電子工程學系碩士論文，2014。

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