透過您的圖書館登入
IP:18.222.183.63
  • 學位論文

通道熱電子注入於非重疊離子植入記憶體元件之電荷分佈研究

Charge profiling of channel hot electron injection in NOI devices

指導教授 : 鄭湘原

摘要


近來來隨著半導體製程的精進與微縮,能儲存多記憶位元於單一 元件內的新型非揮發性記憶體發展,逐漸地受到注目與重視。而相較 於以往利用浮動閘極儲存記憶元的非揮發性記憶體,新型的非揮發性 記憶體更強調在製程上簡化以降低製造成本,因此如何利用現行的標 準邏輯製程開發出新型的多記憶元非揮發性記憶體,為現今各方所努 力的方向與目標。 此論文研究之主題即為一新型嵌入性非揮發記憶體(NOI),除具 有與現行邏輯製程相容之特性,更具有在單一元件內儲存雙位元的優 點。相較於SONOS 是利用閘極介電質中的氮化矽來儲存電荷,NOI 則 是利用氮化矽側壁 (SiN4 Sidewall)來儲存電荷,因此可以解決 SONOS 在元件微縮時所產生的位元合併(Bit-Merging)的問題。 此論文乃首次利用Charge Pumping (CP)來研究電荷於NOI 氮化 矽側壁中的分佈情況,並輔以電腦模擬軟體TSUPREM4 和MEIDI 來佐 證此電荷分佈狀況。從實驗與模擬結果可得知,利用通道熱電子所注 入的電子,在臨界電壓漂移 0.8 伏特(△Vth=0.8V)時, 儲存電荷的 分佈範圍大小約為90nm,且其最大儲存電荷密度的位置乃是靠近汲 極邊界。

並列摘要


Recently, the discrete charge trapping non-volatile memory (NVM) devices received much attention due to their potential multi-bit storage in a unit cell. In contrast to those floating gates memories, oxide-nitride-oxide (ONO) charge trapping structures are explored to store charges in NROM and TwinMONOS for high density NVM devices. Newly developed gate-to-drain non-overlapped implantation (NOI) MOSFETs are proposed by using the silicon nitride (SiN) spacers as charge trapping media. NOI are fully compatible with existing industrial CMOS fabrications without adding process modification and mask tooling cost. Channel hot electron injection (CHEI) and band-to-band hot hole enhanced injection (HHEI) are used to program and erase the NOI device for NVM operations. Novel gate-to-drain non-overlapped implantation (NOI) nMOSFETs have been developed as potential multi-bit-per-cell non-volatile memory (NVM) devices. The lateral charge distribution of the NOI NVM device programmed by channel hot electron injection (CHEI) is investigated by charge pumping (CP) techniques with presumed interface trap distributions. For the first time, the CP results have revealed the lateral charge distribution and trapping density at the NOI’s programmed state (ΔVth=0.8V). The maximum trapping charge density locates near its drain junction. The charge distribution is estimated about 90nm in length and spread widely over the NOI region. 2-D simulators with charge bars using the same charge trapping distribution confirm the experimental results by fitting their IDS-VG curves.

參考文獻


Chapter 1.
Non-Volatile Memory Markets ”, BBC Inc. , July, 2005.
Itoh, ”A new electrically alterable, non-destructive read-only storage
[1.3] W. Johnson, G. Perlegos, A. Renninger, G. Kuhn, and T. Ranganath,
“A 16Kb electrically erasable nonvolatile memory,” IEEE ISSCC

延伸閱讀