同時修復邏輯功能與時序違規之整合ECO方法研究

由於晶片製程技術的日益精進與市場對產品的需求日益增加，現今的晶片設計越來越重視晶片中各個元件的可修復性，在晶片的後端製程(back-end)中，工程變更指令(Engineering Change Order, ECO)是一個常用來修復邏輯功能(functional change)與時序違規(timing violation)的技術，透過元件擺置階段(placement)所散佈的預留邏輯閘(spare cell)，以及修改金屬層(metal layer)的繞線，晶片便可省下大量的製造成本與重新設計的時間。在先前所發表的工程變更指令研究中，我們發現大多數的研究大多分別修復邏輯變更或時序違規，然而我們觀察到先後修復邏輯變更與時序違反的研究方法，可能會產生預留邏輯閘資源爭奪的問題，使得先修復者耗盡晶片上的預留邏輯閘，導致工程變更指令成功率下降，因此在本篇論文中，我們提出一個可同時修復邏輯變更與時脈違反的工程變更指令演算法，藉由所提之虛擬點(virtual node)概念和配對演算法(matching)，來提高工程變更指令的修復成功率。實驗結果顯示，相較於個別修復的研究，本篇論文所提之方法除了可以有效地修復所有工程變更指令外，也使用了較短的修正線長。

關鍵字

工程變更命令；閒置元件；配對演算法；技術印射

並列摘要

Due to the advancement of IC manufacturing and the increasing pressure of time-to-market, the reparability of IC design has become a critical problem. In the back-end design stage, engineering change order is a common technique to repair functional changes and timing violations. By reconnecting original net connections on the metal layer to spare cells which are scattered on the chip during placement stage, the IC manufacturing can save lots of money and time in redesigning ICs or intellectual properties. Although many ECO approaches have been proposed, we find that most of approaches modify functional changes and timing violations separately. However, according to our observation, the separation of two modifications may incur resource competition among spare cells. So that, the first modification may exhaust spare cells and result in ECO failure. Therefore, in this thesis, we propose a unified ECO approach to dealing with functional change and timing violation simultaneously. Through the proposed virtual node insertion and amended matching algorithm, the success rate of ECO can be enhanced. Experimental results consistently show that our approach can effectively fix all ECOs with shorter fixing wirelength.

並列關鍵字

Engineering change order ； spare cell ； matching algorithm ； technology mapping

參考文獻

[3] International Technology Roadmap for Semiconductors: http://www.itrs.net/

[4] A. Balasinski, “Optimization of Sub-100-nm Designs for Mask Cost Reduction”, Journal of Microlithography, Microfabrication, and Microsystems, Vol. 3, No. 2, pp. 322-331, 2004.

[5] Doug Josephson, “The Good, The Bad, and The Ugly of Silicon Debug”, in Proceeding of Design Automation Conference, pp. 3-6, 2006.

[6] R. Goering, “Post-silicon Debugging Worth a Second Look”, EE Times, 2007.

[11] L.P.P.P. van Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay”, in Proceeding of International Symposium on Circuits and Systems, pp. 865-868, 1990.

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同時修復邏輯功能與時序違規之整合ECO方法研究

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