- 學位論文
利用動態光學微影分析進行規則式光學鄰近效 應修正
Rule-Based Optical Proximity Correction Using Dynamic Lithography Analysis
摘要
現今製程技術不斷地進步，元件的尺寸(feature)已小於主要製程光源的波長。而在現有的光刻技術以及製程機台設備下，可製造之最小線寬受到了限制。當線寬小於元件尺寸時，便會導致微影後於晶圓(wafer)上的圖像失真，如橋接、開路或無法成像等問題，使得可製程性下降，晶片的良率與可靠度也隨之降低。藉由光學光刻模擬(Optical lithography simulation)軟體的幫助，設計者可以快速地得知設計線路佈局(layout)的可製程性，並提高製程良率(yield)，遂以修正錯誤的設計。 本篇論文提出Rule-Based光學鄰近效應修正的動態光學微影分析方法，藉由對特定特徵圖形做光學模擬來獲得圖形補償的依據，以提升Rule-Based光學鄰近效應修正的正確率；我們提出圖形完整性考量分割方法，對佈局作分割動作以達到分而制之，並藉由保持圖形的完整幾何資訊，避免傳統分割方法所衍生的鄰邊問題(alignment problem)。另外我們使用分佈式平行處理演算法加速整體運算時間並減少產生搶奪共享資源問題。 由實驗結果顯示測試佈局元件SDFF_X1由原始的點陣圖誤差11.9%降至5%，並且解決原本存在的僑接等成像誤差問題。藉由圖形完整性考量分割方法，相對於無分割方法在耗損時間上平均幾乎減少87%；而再經由分佈式平行處理演算法可再降低幾近48%。
並列摘要
As a result of the manufacturing process continuous improvement, the feature size of IC had been smaller than the wavelength of the mainstream lithography. The smallest feature size is limited according to current lithographic techniques and manufacturing equipment machine. It may cause distortion of printed image on the wafer as gate bridge, open or unable to print on wafer, and leads to manufacturability decreasing, yield loss and reliability dropping. By using optical lithography simulation, designers can easily obtain the manufacturability of layout designs, and increase yield through correcting the design. This paper proposes a dynamic lithography analysis using Rule-Based Optical Proximity Correction method to correct layout with reliable geometry compensation table which could obtain by simulating a series of feature layout pattern in advance. A Grid based Partition approach considering the pattern integrity is propose to achieve divide and conquer, and overcome the alignment problem from conventional partition techniques. In addition, we utilize the technique of distributed parallel process to speed up the program and reduce the possibility of snatching sharing resource. Experimental results on test case of SDFF_X1 show that our algorithm reduces the value of bitmap error from 11.9% to 5%, and solve line bridging and other distortion problems. Through our Grid based Partition approach considering the pattern integrity, the computation time drop down approximately 87% compares to non-partition method. By applying the distributed parallel process we can decrease further 48% of time consumption.