使用多執行緒之平行性自動測試圖樣產生器

Parallel ATPG using Multiple Threads

羅文益(Wen-Yi Luo)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2011年)

https://doi.org/10.6840/cycu201100623

摘要

在本篇論文中，我們使用具有多核心處理器之電腦，利用多執行緒(multiple threads)觀念，以平行處理方式進行自動測試圖樣產生(automatic test pattern generation)之程序。平行處理的方法主要是採用動態式障礙分割(dynamic fault partitioning)之架構，每個處理器核心會依據產生測試圖樣過程中，是否已有新產生的測試圖樣，決定執行圖樣產生(test generation)或障礙模擬(fault simulation)，如此可以增加核心的執行效率，進而提升整體平行處理的速度。另外我們也在平行處理的前端作業中，加入隨機測試圖樣的產生，並以平行之障礙模擬方式，尋找有效之隨機測試圖樣，如此可以更快完成平行測試圖樣產生過程。在找完測試圖樣後，我們將圖樣進行靜態壓縮(static compression)，減少因平行處理而產生之多餘測試圖樣。我們採用ISCAS’89標準測試電路進行實驗，結果顯示所提方式確實可以有效提升測試圖樣產生之速度。

關鍵字

多核心 ； 平行處理 ； 多執行緒

並列摘要

In this thesis, we present a method of parallelly generating test patterns for stuck-at faults. The method uses multiple threads in the system of multi-core processors. We primarily use dynamic fault partitioning for the parallel ATPG. During the process, each thread can decide by itself to generate a new pattern or to run fault simulation for a newly generated pattern. In this way, we can speed up the pattern generation and therefre improve the efficiency of parallel ATPG. In addition, we incorporate parallelly generating random patterns and simulating them in the beginning of parallel ATPG to further speed up the whole process. We also use static compaction to reduce the amount of finally obtained patterns. We experiment on the ISCAS'89 benchmark circuits to show the efficiency of proposed method. The results show that our multi-thread ATPG can really speed up the complete process of pattern generation.

並列關鍵字

multi-threads ； parallel computing ； multi-cores

參考文獻

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