非重疊佈值場效電晶體電荷可靠度模型探討

Study of Charge Retention Reliability Model in Non-overlapped Implantation nMOSFETs

蕭智祥(Chih-Hsiang Hsiao)

指導教授 ： 鄭湘原

中原大學/工學院/電子工程研究所/碩士(2012年)

https://doi.org/10.6840/cycu201201045

摘要

隨著半導體製程技術的精進與可攜式產品的廣泛運用，非揮發性記憶體在半導體記憶元件中所扮演的角色越來越重要。在元件持續微縮的情況下，講究具有功率消耗低、元件密度高、操作速度快、且相容於CMOS製程等特色的記憶元件將是未來發展的趨勢。
本論文以熱電子注入對非重疊佈植記憶元件之資料保存做為研究主題，此記憶元件的寫入係利用通道熱電子注入，並以兩側壁區作為個別位元儲存之區域。透過Arrhenius equation預測高溫下元件特性於短時間內的變化。並藉由實際的電荷幫浦(Charge Pumping)實驗量測與計算電荷流失狀況。最後，配合理論推算及量測結果去探討記憶元件資料保存特性。

關鍵字

電荷幫浦 ； 非揮發性記憶體 ； 資料保存

並列摘要

The non-volatile semiconductor memories play more and more important roles as the device technology advances and the portable products rapidly progress. The development of memory devices having low power consumption, high density, high-speed operation, and full compatibility with the standard CMOS processing will an important topic in non-volatile memories.
This work explores the data retention of trapped electrons in the Non-overlapped Implantation (NOI) MOSFETs. As potential non-volatile memories, the NOI devices can be programmed by channel hot electron injection. The charges can be trapped in the NOI’s nitride spacers by Arrhenius equation, the charge loss in spacers with time has been modeled under high temperatures. The charge loss in the nitride was also measured using a modified charge pumping method. Finally, the Vth and charge pump results are explored for analyzing the data retention characteristics of the NOI MOSFETs.

並列關鍵字

charge pumping ； data retention ； NVM

參考文獻

Chapter 1

[1-2] W. D. Brown, and J. E. Brewer, Nonvolatile Semiconductor Memory Technology, IEEE Press, 1998.

[1-4] W. D. Brown, and J. E. Brewer, Nonvolatile Semiconductor Memory Technology, IEEE Press, 1998.

[2-1] H. Lee, S. Chang, J. Lee and H. Shin, “Characteristics of MOSFET with Non-overlapped Source-drain to Gate”, IEICE Trans. Electron, Vol. E85-C, No. 5, pp. 1079-1085, 2002.

[2-2] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Lett., Vol.21, No. 11, pp. 543–545, Nov. 2000.