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  • 學位論文

採用機器學習評估靜態時序分析之研究

Study of Machine Learning Methodology for Static Timing Analysis

指導教授 : 鄭維凱
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摘要


在IC 設計中Timing 分析是一個重要的環節,不僅能判斷Chip是否能正常work,同時也很衡量Chip的重要性能的關鍵,在實體設計階段會使用Timing analysis的方式去分析Chip在實體設計階段是否有符合Designer的設計規劃,同時也是Physical design engineer判斷設計過程是否符合預期的重要指標之一。常用的Timing analysis有static 與 dynamic兩種,其中在設計階段最常使用的是Static Timing Analysis簡稱(STA)。值得注意的是Physical design tool 都能自動協助Physical design engineer收斂70%的Timing問題,仍有30%的問題是需要仰賴Physical design engineer花費冗長的迭代時間去人工處理,這樣的過程會出現很多狀況導致整個晶片設計周期延長,這再晶片設計領域對產品競爭力無疑是一個打擊,因此本文提出導入Machine Learning 的技術,期望透過提取Design的部分資訊與Physical design tool中的部分資訊作為Feature,並進行Training得到一個能夠有效回饋給Physical design engineer 收斂Timing的機制Model。

並列摘要


Timing analysis is an important link of IC design. It’s not only judging whether Chip will work normally but also measuring the important performance of Chip. In the physical design stage, Timing analysis will be used as analyze the chip's physical design. Whether the stage has a design plan that complies with the Designer is also one of the important indicators for the Physical design engineer to judge whether the design process is in line with expectations. There are two commonly used Timing analyses, static and dynamic, of which Static Timing Analysis abbreviation (STA) is most commonly used in the design phase. It is worth noting that the Physical design tool can automatically assist the Physical design engineer to converge 70% of the Timing problem. There are still 30% of the problems that need to be handled manually by the Physical design engineer for a long iterative time. This process will cause many situations. The entire chip design cycle is prolonged. This is undoubtedly a blow to product competitiveness in the field of chip design. Therefore, this article proposes to introduce the technology of Machine Learning, hoping to extract part of the information from Design and part of the information from the Physical design tool as a Feature and conduct training. Obtain a mechanism Model that can effectively feedback to the Physical design engineer to converge Timing.

參考文獻


[1] L. Chen, C. Huang, Y. Chang, and H. Chen, “A learning-based methodology for routability prediction in placement,” in 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1–4, 2018.
[2] A. F. Tabrizi, N. K. Darav, L. Rakai, I. Bustany, A. Kennings, and L. Behjat, “EhPredictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 6, pp. 1177–1190, 2020
[3] Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, and Jiang Hu. Routenet: Routability prediction for mixed-size designs using convolutional neural network. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–8. IEEE, 2018.
[4] ISPD 2006 ACM International Symposium on Physical Design, 2006.
[5] Z. Qi, Y. Cai, and Q. Zhou, “Accurate prediction of detailed routing congestion using supervised data learning,” in 2014 IEEE 32nd International Conference on Computer Design (ICCD), pp. 97–103, 2014.

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