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  • 學位論文

熱導向之功能運算單元繫結問題研究

A Formal Approach to the Heat - Driven Functional Unit Binding in High Level Synthesis

指導教授 : 黃世旭

摘要


當IC製程已步入深次微米之技術,設計的複雜度也相對提升。因此一個最新的超大型積體電路晶片的溫度消耗也急速地提升。在本文中,我們研究以解決溫度散逸為目標的功能運算單元繫結問題。眾所皆知的,假設對於同一個功能運算單元在兩次連續的運算執行之間有越多的閒置時間間隔,此功能運算單元執行時的溫度將可降低越多。因此,給定一個已排序的控制/資料流程圖(CDFG)及功能運算單元,為了達到最低溫度散逸的功能運算單元繫結結果,我們的目標即是最大化閒置時間間隔的總和。我們提出一個整數線性規劃的方法正式地描述此問題。實驗結果顯示我們提出的方法在可接受的執行時間內確實達到溫度最小化之目的。

並列摘要


As the process shrinks into the deep sub - micron technology, the design complexity continues to increase. Therefore, the heat dissipation in a modern VLSI chip is skyrocketing. In this paper, we study the functional unit binding for heat dissipation. It is well known that, if there is more inactive time interval between two consecutive operations executing in the same functional unit, the more heat reduction can be achieved. Therefore, given a scheduled control/data flow graph (CDFG) and the functional units, our objective is to maximize the summation of inactive time intervals. An integer linear programming (ILP) approach is proposed to formally formulate this problem. Benchmark data consistently show our approach achieves good results within an acceptable run time.

參考文獻


[2]Chen, C., & Sarrafzadeh, M. "Power Management Scheduling Technique for Control Dominated High Level Synthesis." Proc. of IEEE Design, Automation and Test in Europe Conference and Exhibition, pp. 1016 - 1020, 2002.
[4]Huang, W., et al. "Compact Thermal Modeling for Temperature-Aware Design." Design Automation Conference, pp. 878 - 883, 2004.
[5]Liao, W., F. Lei, & L. He. "Microarchitecture Level Power and Thermal Simulation Considering Temperature Dependent Leakage Model." International Symposium on Low Power Electronics and Design, pp. 211 - 216, 2003.
[8]Tsai, C., & Kang, S. "Standard Cell Placement for Even On - Chip Thermal Distribution." International Symposium on Physical Design, pp. 179 - 184, 1999.
[11]Basu, A., Lin, S.C., Wason, V., Mehrotra, A., & Banerjee, K.. "Simultaneous Optimization of Supply and Threshold Voltages for Low - Power and High - Performance Circuits in the Leakage Dominant Era." Proc. of IEEE/ACM Design Automation Conference, pp. 884 - 887, 2004.

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