多行程調參及效能優化之功能性工程變更指令方法

Functional ECO Method with Multi-Process Parameters Tuning and Performance Optimization

陳立穎(LI-YING CHEN)

指導教授 ： 梁新聰

中原大學/電機資訊學院/電子工程學系/碩士(2022年)

https://doi.org/10.6840/cycu202201355

摘要

在VLSI設計流程的後期，如果發現設計錯誤需要修改，功能性工程變更指令(Engineering Change Order, ECO)是一種被普遍使用的方法。本論文提出一個多行程(multiprocessing)調參及效能優化之功能性工程變更指令方法來修正電路設計錯誤。我們使用的功能性工程變更指令演算法透過使用FRAIG演算法、切割匹配(Cut Matching)演算法以及電路相似度來生成最小修補。然而，此演算法的結果受參數設定影響，因此我們使用多行程調整參數演算法執行各組參數來取得最佳結果。接著我們再進一步做效能優化使得演算法的效能更為優異。實驗結果證明我們提出的方法能產生較小的修補檔以及提升效能。

關鍵字

型式驗證 ； 等價性檢查 ； 功能性工程變更指令 ； 效能優化 ； 多行程

並列摘要

Functional engineering change order is a popular approach for rectifying circuit design errors in late VLSI design stages. In this thesis, we present a Functional ECO Method with Multi-Process Parameters Tuning and Performance Optimization to rectify design errors. Our functional ECO engine generates minimal patch by using FRAIG algorithm, the cut-matching algorithm and the circuit similarity information. However, the result of this ECO engine is affected by the parameters setting, so we use a multi-process parameters tuning algorithm to execute each set of parameters to get the best result. Then we do performance optimization to improve the performance of our algorithm. Experimental results show that our method can generate smaller patches to rectify circuit and optimize performance.

並列關鍵字

Formal Verification ； Equivalence Checking ； Functional Engineering Change Order ； Performance Optimization ； Multiprocessing

參考文獻

[1] Yen-Chun Fang, Shao-Lun Huang, Chi-An (Rocky) Wu, Chung-Han Chou, Chih-Jen (Jacky) Hsu, WoeiTzy (Wells) Jong, and Kei-Yong Khoo, “2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance”, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 6 pages, 1-4 Nov. 2021.

[2] github.com/HHHUUUGGGOOO/CAD_Contest_A_2021

[3] www.eettaiwan.com/20190715ta31-introduction-to-formal-verification/

[4] Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, and Chung-Yang (Ric) Huang, “Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(3), 467–478, March 2013.

[5] Vinicius Neves Possani, “Parallel Algorithms for Scalable Logic Synthesis & Verification”, PhD thesis, pp. 7-106, Universidade Federal do Rio Grande do Sul. Programa de Pós-Graduação em Computação, Porto Alegre, Brazil, April 2019.