應用於影像拼接之基於影像融合演算法去塊效應濾波器晶片設計

Deblocking Filter Chip Design Based on Image Fusion Algorithm for Image Stitching

陳姿伃(TZU-YU CHEN)

指導教授 ： 陳世綸

中原大學/電機資訊學院/電子工程學系/碩士(2022年)

https://doi.org/10.6840/cycu202201545

摘要

隨著現今科技發展，人們生活中充滿著越來越多基於影像處理相關的電子產品。例如，以環繞視圖相關係統開發的汽車顯示器等。因此，本論文中介紹一種基於圖像融合技術的去塊效應濾波器之晶片電路設計，將其用以改進適用於環視系統應用的拼接圖像。本論文提出的去塊效應濾波器之晶片電路設計不僅適用於與電子相關的各種成像產品的全景圖像上，而且在晶片電路設計上也實現了這項技術。為了減少全景拼接上可見的偽影，達到視覺上不明顯接縫的效果，本論文提出創新高分辨率環視系統為目標。相較於將拼接圖像分成超過 16x16 個單元塊的 H.264 和 H.265 去塊效應濾波器，本論文中提出的去塊效應濾波器之晶片電路設計是將拼接圖像中的 P 塊和 Q 塊的兩個圖像分成四個單元塊。同時於邊界條件部分由BS=0~2簡化為BS=1和BS=2共兩項篩選條件。
在硬體上，本論文針對需要經過去塊效應濾波器固定的像素，簡化拼接圖像中的塊範圍劃分。並且邊界條件部分也簡化了過濾條件部分的架構。透過本論文提出簡化架構的方法後，可有效將計算複雜度降低，並提高運算速度。此晶片電路設計除了減少輸入和輸出的腳位，以及將晶片面積縮小至387,446μm2之外，其中也包含了11.153個邏輯閘和功率消耗為43.7 mW。而這些條件在硬件架構上皆有利於減少硬體消耗的資源以降低晶片生產所消耗之成本。因此，本論文運用此方法實際設計出一種新的去塊效應濾波器之晶片。

關鍵字

去塊效應濾波器 ； 影像融合

並列摘要

With the nowadays development of the technology, there are more and more electronic products based on image processing in people's lives. For example, the automotive screens are developed for surrounding view related systems. Therefore, this thesis describes a deblocking filter chip design based on image fusion technique to improve the stitched image for surrounding view system applications. It not only applies to panoramic images for each imaging product that relates to electronics, but also realizes this technology on a chip. To reduce visible artifacts on the panoramic stitching and achieve the effect of visually not obvious seams are the targets which is created a high-resolution surrounding view system in this thesis. Compared to the H.264 and the H.265 deblocking filters which divide the stitching images into more than 16x16 cell-blocks, the proposed filter divides two images of the P block and Q block into four cell-blocks for the filter. At the same time, the part of the boundary condition is simplified from BS=0~2 to BS=1 and BS=2.
In terms of hardware, this thesis simplifies the block range division in the stitching image for the pixels which need to be fixed by the deblocking filter. And the part of the boundary condition has also simplified the architecture in the filtering conditions part. After this thesis simplifies the architecture, it can effectively reduce the computational complexity and improve the operative speed. In addition to reducing the number of the input and the output pins and reducing the chip area to 387,446μm2 in the chip circuit design, it also contains 11.153 gate counts and a power consumption of 43.7 mW. These conditions are conducive to reduce the resources consumed and the cost of chip production in the hardware architecture. Therefore, this thesis designs a novel chip for the new deblocking filter.

並列關鍵字

Deblocking Filter ； Image Fusion

參考文獻

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