功率限制下共同進行記憶體內建自我測試控制器分組及測試排程最佳化

Co-Optimization of Memory BIST Grouping and Test Scheduling under Power Constraints

葉昌翰(Chang-Han Yeh)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2016年)

https://doi.org/10.6840/cycu201600694

摘要

內建自我測試電路為目前的主流技術，解決嵌入式記憶體驗證和修正問題，隨著晶片的設計更複雜所造成測試時間也就更長，測試時間又直接影響測試成本。除了測試時間外，內建自我測試電路所消耗的面積、內建自我測試控制器和記憶體繞線長度也須納入成本的考量。這篇論文中，我們提出混合整數線性規劃(Mixed Integer Linear Programming)的方法，我們的目標在功率限制線最佳化整體測試時間，並同時考慮內建自我測試控制器數以及內建自我測試控制器和記憶體距離。實驗結果顯示我們提出的方法，可以達到最小化總測試時間長度並提高測試效率降低成本的目標。

關鍵字

記憶體測試排程、內建議我測試電路、記憶體分群、整數線性規劃

並列摘要

Built-in self-test (BIST) is a well-known design technique for the embedded memory verification and fixing problem. As the chip design becomes more complex, the test time also becomes longer, which directly affects the cost of the testing. In addition to the test time, the built-in self-test circuit area, built-in self-test controller and memory routing wire length should also be included in the cost considerations. In this thesis, we propose a mixed integer linear programming approach to optimize the total test time under power constraints by taking into account the number of built-in self-test controller as well as the distances between BIST controller and memories. Experimental results show that our proposed method can achieve the minimum total test time and improve test efficiency by reducing the costs.

並列關鍵字

Memory Testing, Built-in-self-test (BIST), Test Scheduling, Grouping, Integer Linear Programming.

參考文獻

[31] S.H. Huang, C.H. Chiu, C.H. Cheng, T.J. Wang, "Simultaneous Test Scheduling and TAM Bus Wire Assignment for Temperature-Dependent Core-Based SoC Testing ", International Journal of Electrical Engineering (IJEE), vol. 23, no. 4, pp. 53-62, 2016.

[2] Miyazaki, Masahide, Tomokazu Yoneda, and Hideo Fujiwara. "A memory grouping method for sharing memory BIST logic." Asia and South Pacific Conference on Design Automation, 2006.. IEEE, 2006.

[5] Zorian, Yervant. "A distributed BIST control scheme for complex VLSI devices." VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE. IEEE, 1993.

[6] Bodoni, M. Lobetti, et al. "An effective distributed BIST architecture for RAMs." Test Workshop, 2000. Proceedings. IEEE European. IEEE, 2000.

[7] Nicolici, Nicola, et al. "BIST hardware synthesis for RTL data paths based on test compatibility classes." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19.11 (2000): 1375-1385.