功率消耗與測試墊限制下之三維積體電路測試排程問題研究

3D IC Test Scheduling under Power and Test Pads Constraints

許銘軒(Ming-Hsuan Hsu)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2016年)

https://doi.org/10.6840/cycu201600695

摘要

隨著晶片的設計越來越複雜，三維積體電路(Three-Dimensional Integrated Circuits, 3D ICs)逐漸變成一種設計趨勢；然而在測試三維積體電路方面也相較於傳統電路複雜。與傳統的系統晶片測試相同，三維積體電路的功能核心會經由TAM Bus連接至外部測試機台(ATE)來做測試，不過在3D IC中，測試會分成兩個部分:pre-bond與post-bond測試，因此TAM Bus的分配與測試墊(Test Pad)的運用會更加複雜。因此在測試墊的數目與功率消耗限制下，如何有效運用TAM Bus分配以最小化整體測試排程的時間是我們研究目標。
在本篇文章中，我們提出整數線性規劃(Integer Linear Programming)方法來達到在功率消耗與測試墊數目的限制下，最小化整體測試時間。與過去的文獻比較，我們的方法能更有效的減少測試墊的數目並且同時最小化三維積體電路整體測試時間。

關鍵字

三維積體電路 ； 測試排程 ； 測試墊 ； TAM Bus分配。

並列摘要

As the system-on-chip (SoC) design complexity continue to increase, three-dimensional integrated circuit (3D IC) design has become an industry trend. However, the testing of a 3D IC is more difficult than the testing of a 2D IC. As the same as a 2D IC, the core of a 3D IC must use the TAM Bus to connect with the automatic test equipment (ATE). But in for a 3D IC, its testing includes two parts: pre-bond testing and post-bond testing. The decision on the assignment of test access mechanism (TAM) Bus and the number of test pads of each layer becomes more complicated. Thus, our objective is to minimize the total test time of the 3D IC under the constraints on power consumption and the constraints on the number of test pad.
In this thesis, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling under test pads and peak power constraints. Different from previous works, our approach can minimize both test application time and the number of required test pads. Experimental results show that our approach achieves better results than previous works.

並列關鍵字

Three-dimensional (3D) integrated circuit (IC) ； test Scheduling ； test pads ； test time ； test access mechanism (TAM) bus assignment.

參考文獻

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