以切割為基礎之平行化光學鄰近效應修正方法

隨著製程技術不斷的進步，積體電路的特徵尺寸(feature size)不斷的縮小，使得光罩上圖形(pattern)的線寬小於光刻技術中主要光源的波長，所以在光學微影的階段，光學鄰近效應(Optical Proximity Effect)的影響更加明顯，而導致良率下降。現今有很多解析度增強技術(Resolution enhancement technology)已被廣泛地使用，目的是要達到減少光刻過程所帶來的負面影響，如電子束微影技術(Electron-Bean Direct Write)、光學鄰近修正(Optical Proximity Correction, OPC)。光學鄰近修正是一種常用來改善光罩圖形失真問題的光學光刻方法，可以藉由它來補償原始的光罩圖形，使得在經過光罩曝光後可得到預期的成像。規則式OPC(Rule-based OPC)以及模型式OPC(Model-based OPC)是現今兩個主要的解析度增強技術；規則式OPC是藉由取得圖形特徵的可靠幾何數據，再以查表的方式對整體佈局進行修正，此方法較為快速；而模型式OPC則會考慮許多的製程參數以及光學參數來對佈局圖形做光學模擬，並且反覆地對圖形做修正，直到得出優化的結果為止，此方法需耗費大量的計算時間，但有較佳的可靠度以及精確度。本論文以模型式OPC(Model-based OPC)光罩修正方法；並結合規則式OPC與模型式OPC的熱點(hotspot)分析以提升光學微影成像解析度，依照不同區塊內圖形的複雜度，進行區塊的合併，使得要修正的區塊有較相近的複雜度，以利於平行化。本論文也採用多執行緒的方式執行程式，可以有效地加速。實驗結果顯示，以多執行緒的方式執行程式，每個case的時間都有很明顯的改善，使用多個Thread方式去執行，時間都可以縮短1.9~4倍的時間。

關鍵字

平行化；圖形切割；光學鄰近效應修正；光學模擬

並列摘要

As the nanometer manufacturing process constantly making progress, the feature size of integrated circuit has been shank. It makes the size of mask pattern smaller than the wavelength of the major lithography light. Hence the optical proximity effect has became more significantly worse, and result in yield loss. For the purpose of reducing the optical proximity effect and achieving the better IC yield, there are lots of Resolution Enhancement Technology(RET) has been widely used, such as Electron Beam Lithography(EBL)、Optical Proximity Correction (OPC),etc. OPC is generally used to improve the mask pattern distortion. By compensating the original mask, IC designer can achieve the expected imaging easily. Rule-based OPC and model-based OPC are now the two major resolution enhancement technology. There are the two main ways of OPC. The first way is Rule-based OPC is a simpler technique which is to obtain the reliable geometry data of the pattern features, and then apply to the layout mask by looking up the bias table. The other way is model-based OPC, it considers several process effects and optical parameters to simulate the layout pattern and apply a feedback system back and forth to end up with an optimal result. This way is more complex and time-consuming, but the reliability and accuracy of the result will significantly improve. In this paper, we extend the previous work [26] and proposed a hybrid OPC with partition process. By adopting the advantage of two OPC technique, we can enhance the resolution of lithography. According to the complexity of sub-region of the mask, we can merge those sub-regions which have lower complexity and make all sub-regions have approximate complexity. After that those sub-region can easily apply to multi-threading. The experimental results show that all cases have been improved significantly, the runtime can be shortened between 1.9 ~ 4 times.

並列關鍵字

Parallel ； Partition-based ； Optical simulation ； OPC

參考文獻

[1]M.D. Stewart, G.M. Schmid, S.V. Postnikov, C.G. Willson, “Mechanistic Understanding of Line-End Shortening ”, Proc. of SPIE, pp.10-18, 2001.

[2]S. Sivakumar, “Lithography Challenges for 32nm Technologies and Beyond”, Proc. of IEDM, pp. 1-4, 2006.

[3]L.R. Harriott, “Limits of lithography”, Proc. of IEEE, pp. 336-374, 2002.

[6]Y. Wang, Y. Cai, X. Hong and Q. Zhou. “Algorithm for yield driven correction of layout”, Proc. of ISCAS, V-241- V-245 Vol. 5, 2004.

[7]K. Cao and J. Hu, “ASIC design flow considering lithography-induced effects”, Proc. of Circuits, Devices &Systems, IET, vol. 2, pp.23-29, 2008

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以切割為基礎之平行化光學鄰近效應修正方法

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