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  • 學位論文

即時可重新架構桶狀及枕型失真校正影像處理器設計

Time Multiplexed Reconfigurable Barrel and Pincushion Corrector Design for Real-Time Applications

指導教授 : 陳世綸

摘要


本篇論文提出一個低成本之即時可重新架構桶狀及枕型失真校正影像處理器,校正失真影像是廣泛應用在許多應用中,所以影像校正為一重要且必須之技術。在此論文中,提出一個可以校正桶狀失真及枕型失真的可重新架構影像處理器,為了達到可以將失真影像即時校正還原,在電路設計中加入了pipeline技術去縮短整個電路的最長路徑,以提高電路的速度進而達到能即時處理影像之需求。而為了更進一步減少電路成本、運算量及硬體中記憶體的需求量,Hornor’s algorithm、時間多工的選擇及硬體共用等技術皆被使用在此設計中,因為可重新架構之設計,使用同一個積體電路設計之硬體可校正桶狀及枕型兩種不同的失真影像。在積體電路設計中,我們使用台積電0.18-μm CMOS之製成,達到使用8.6K gate counts 完成此電路。與其他先前的研究相比,不但可以不利用額外的校正公式即可校正兩種失真影像,同時節省了37.75%的gate counts成本。

並列摘要


In this thesis, a low-cost VLSI circuit is proposed for reconfigurable barrel and pincushion correction for real-time video application. Distortion correction technologies are necessary and widely used in many applications. In this thesis, a reconfigurable structure is proposed for correcting in terms of a barrel and pincushion distortions. In order to achieve correcting the distortion images in real-time, a pipelined technique was used to shorten the critical path of the proposed VLSI architecture. Furthermore, a Hornor’s algorithm, time multiplexing, and hardware sharing techniques were used to decrease the computing resource, hardware cost, and memory requirement. By using reconfigurable technique, this thesis can correct two different types of distorted images, barrel and pincushion distortions, by only one VLSI design. The VLSI architecture of this design contains 8.6-K gate counts by a 0.18-μm CMOS process. Compared with previous studies, this thesis not only reduces at least 37.75 % hardware cost but also provides one more distortion correcting function.

參考文獻


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