以差動差分電流傳輸器為主動元件設計 電壓式四階低通濾波器

Voltage-Mode Fourth-Order Low-Pass Filter Employing Four DDCCs

林至亮(Chih-Liang Lin)

指導教授 ： 張俊明

中原大學/工學院/電機工程研究所/碩士(2009年)

https://doi.org/10.6840/cycu200900771

摘要

以往設計的電路為了追求輸出訊號的準確度或彌補電路中的缺失而加上許多補償電路，使得電路複雜化、龐大化。而在電路積體化的同時，導線之間的距離隨著製程技術的進步而愈來愈靠近，也更容易發生寄生效應的問題，導致輸出信號有誤差。為了減少寄生效應，在電路設計上必須以最少之節點數目，也就是使用最少的主被動元件為原則，以達到精準的輸出信號。當我們使用最少的主被動元件來設計電路時，能降低電路的功率消耗，在製成IC時雜訊減少、面積變小，且成本可以降低，故本文所提出的電路以此原則為設計目標。
近年來學者常以電流式主動元件設計類比電路，因為以電流式主動元件所設計的電路，具有頻寬大、線性範圍大、功率損耗小、電路簡單等優點。本文所提出之電路主要使用一種特別的電流式主動元件：差動差分電流傳輸器(Differential Difference Current Conveyor，以下簡稱DDCC)來設計電壓式四階低通濾波電路。本電路使用最少的被動元件(四個接地電阻及四個接地電容)，並對電路作非理想分析，探討影響輸出信號準確度的因素，再利用所求的被動元件對頻率響應的敏感度分析，調整被動元件的大小，以提高輸出信號的準確度，之後再對以電流傳輸器為主動元件之電壓式低通濾波電路進行比較。
最後，本論文所提之電路以H-SPICE軟體進行電路模擬，使用之製程參數為TSMC035μm。並以MATLAB軟體進行理論上的驗證，藉此比較理論與實際模擬結果之間輸出信號的差異。

關鍵字

電壓式 ； 低通 ； 濾波器 ； 電流傳輸器

並列摘要

Formerly designed in electric circuit, in order to output finer or makes up the electric circuit flaw addition to more compensating circuits, causes the electric circuit complication and bulky. However, while the circuits get integrated, there will be narrower space between wires with the advanced technologies, and this will result in more parasitic effects and errors of output signals. In order to reduce the parasitic effects, the circuit with minimum numbers of nodes is a must, that is, we should minimize active elements and passive elements to make output signal more precise. When we design circuits use minimum numbers of active elements and passive elements, can reduce power consumption of electric circuits. Also during the IC process producing, the noise of chips can be decreased, the chip area can be smaller, and the cost can be cut down. Hence, the proposed circuit takes this principle as circuit design goal.

It has been verified that the circuits constructed by active current-mode elements have the advantages of higher signal bandwidths, greater linearity, less power dissipation and simpler circuit structure. The circuit we talk about on this paper uses one special active elements, namely, differential difference current conveyors (DDCCs) to design the voltage-mode high-order low-pass filter. In addition, we use the minimum number of passive components (four grounded capacitors and four grounded resistors) and consider the non-ideal effect. Therefore, we analyze the sensitivity of the passive elements and make output finer by tuning passive elements. Afterward we compare with voltage-mode low-pass filters used current conveyors .

Finally, the simulation of this paper uses H-spice with TSMC035 process to obtain the results. By using MATLAB to testify the theoretical predictions, we can observe the difference between theoretical parts and simulation parts.

並列關鍵字

voltage mode ； DDCC ； Differential Difference Current Conveyor ； filter ； low-pass

參考文獻

[1] B. Wilson, “Recent developments in current conveyors and current- mode circuits”, Proc. Inst. Elect. Eng., Pt. G, vol. 137, no. 2, pp. 63-77, 1990

[2] K. C. Smith, and A. Sedra, “The current conveyor - a new circuitbuiding block”, IEEE Proc., 56, pp.1368-1369, 1968.

[3] K. C. Smith, and A. Sedra, “A second-generation current conveyor and it's applications”, IEEE Trans., CT-17, pp.132-134, 1970.

[4] A. Fabre, “Third-generation current conveyor”, Electronics Letters, vol. 31, no. 5, pp. 338-339, 1995

[5] H. O. Elwan, and A. M. Soliman, “Novel CMOS differential voltage current conveyor and its applications,” IEE Proc.-Circuit Device Syst., 144,(3),pp.195-200,1997.