本研究的目的是從曝光製程著手,利用半遮蓋的方式設計光罩,使透過的光產生繞射(Diffraction)及干涉(interference)的作用,於是在曝光的過程將會造成不同的能量分佈區域,使部分位置的光阻劑因為接受能量較低而曝光不完全,經顯影後則呈現與周圍完全受光的光阻有不同厚度的光阻殘留(PR remain)差異。我們利用此技術可以把製作薄膜電晶體陣列的第二道曝光製程與第三道曝光製程合併,只需曝光一次,再配合蝕刻製程的順序調整,即可將傳統式的五道光罩簡化成四道光罩的製程,但是仍然能維持原本的薄膜電晶體元件之電性特性。本實驗係以半遮光罩的線寬(Line)與狹縫寬度(Space)為參數,由所蒐集的全部光罩設計的組合實驗數據中,挑選出製程條件較佳的光罩結構配置為固定Line 1.0μm 、 Space 1.2 ~ 1.5μm,再調整單位曝光量所產生對PR remain約有800 Å的變動量,因此可以建立四道光罩製程的關鍵配方(Recipe),便於將來導入新的製程時,可以做為工程師即時判斷的依據,使快速達成量產的目標。此外,由於少了一道曝光製程,可節省1~2台的曝光機資本支出,製程的Cycle Time也由七天縮短為五天,等於減少了生產線上20%的在製品流竄,以致可降低庫存的成本與不良品的機率。
A half-cover mask technology is studied for the simplification of thin film transistor (TFT) array process. Based on the principle of diffraction and interference, the light transmitted through the mask results in energy dispersion during the exposure process. As a result, under-exposed regions contain photo-resist remains after development when compared to well-exposed regions. By using this technique and adjusting the sequences of etching process properly, only one exposure can be used instead of the original second and third exposure procedures in the traditional TFT array process and still keep the electrical characteristics of TFT array. Experiments were carried out by adhering to key parameters of line width and slit space of the half-cover mask. Experimental results show that the current optimization combination is a line width of 1.0μm with a slit space of 1.2 ~ 1.5μm which results in a 800Å variation of PR remain via adjusting a suitable unit dose. Hence, a recipe of four-mask process can be constructed instead of traditional five-mask process. This experiment can be applied to the mass production targets for the import of new process in future. In addition, this technique reduces the exposure times which save the cost of exposure machinery and reduces the cycle time from seven to five days. This lowers approximately twenty percent of in-process product ratio and saves reserving costs and reduces irregular product risk.