應用於振盪電路之非同步數位介面與可程式燒錄收發器積體電路設計

本論文之目標為開發鎖相迴路頻率校正晶片，此晶片是由類比積體電路與數位積體電路所構成的，其中在數位積體電路部分是由1.非揮發性記憶體，其用途是儲存各類比電路的參數2.鎖相迴路頻率校準系統，接收外部指令達到Trim value及改變晶片的功能3.非同部介面積體電路設計，為確保鎖相迴路與頻率校準系統之間的資料傳輸正確，本論文將採用非同步介面的技術來有效處理訊號操作頻率不同的問題4.三線式的串列通訊協定，由於鎖相迴路產品的晶片面積十分小，因此為了避免面積受限於腳位過多的缺點，在腳位的設計上必須最十分完整的考量。本論文希望藉由這次所完成的鎖相迴路頻率校準系統，與內部鎖相迴路類比電路結合，搭配本論文建立的可程式燒錄驗證系統，在數位訊號技術方面會使用到SPI (serial peripheral interface)的串列傳輸模式，其中包括串並列資料轉換、匯流排時序控制，利用在工作站的Verilog硬體語言，燒錄進FPGA開發板上，編譯及佈線完成之後，用此技術搭配正確的訊號波形與升壓技術進入此產品，對晶片進行串列資料的燒錄，再利用示波器與邏輯分析儀，驗證此系統是否正確，準確校準晶片到所需之時脈頻率。

關鍵字

FPGA燒錄器；非同步數位介面；時脈效正系統

並列摘要

The purpose of this thesis is to develop a phase-locked loop frequency correction chip. This chip is composed by analog integrated circuits and digital integrated circuits. This thesis has completed digital integrated circuit part - phase-locked loop frequency calibration algorithm (storage the analog parameter), phase-locked loop frequency calibration system (receive external commands to reach “trim value” and change the function of the chip), asynchronous interface design (operating frequency different between chip and programmable transceiver), minimization of the number of input / output pad (three wires of serial peripheral interface) and a programmable logic array verification system development This thesis develops phase-locked loop diagram of the product architecture. Moreover, the digital programmable transceiver will be designed to serial transmission mode with the FPGA development board. The FPGA was designed by the hardware description language. By this design, the transceiver uses this serial transmission with the boost technology to communicate with chip and then use an oscilloscope and logic analyzer to verify the correctness of the system

並列關鍵字

calibration system ； Asynchronous ； Parallel ； Serial ； Digital interface

參考文獻

[1] K. Souri, M. Kashmiri, and K. Makinwa, “A CMOS temperature sensor with an energy-efficient zoom ADC and an inaccuracy of ±0.25°C (3σ) from -40°C to 125°C,” IEEE ISSCC Dig. Tech. Papers, pp. 310–311, Feb. 2010.

[2] Y. S. Lin, D. Sylvester, and D. Blaauw, “An ultra-low power 1V, 220nW temperature sensor for passive wireless applications,” Proc. CICC, pp. 507-510, Sept. 2008.

[3] I. M. Filanovsky and A. Allam, “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,” IEEE TCAS-I, vol. 48, pp. 876-884, July 2001.

[4] F. Sebastiano et al., “A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from –70°C to 125°C,” IEEE ISSCC Dig. Tech. Papers, pp. 312-313, Feb. 2010.

[5] Y. W. Li et al., “A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS,” IEEE ISSCC Dig. Tech.Papers, pp. 340-341, Feb. 2009.

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應用於振盪電路之非同步數位介面與可程式燒錄收發器積體電路設計

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