以差動差分電流傳輸器及完全差分電流傳輸器設計三階與六階帶拒濾波電路

Design of Third-Order and Sixth-Order Band Reject Filters Using DDCC(s) and a Single FDCCII

廖家毓(Chia-Yu Liao)

指導教授 ： 張俊明

中原大學/工學院/電機工程研究所/碩士(2014年)

https://doi.org/10.6840/cycu201400601

摘要

摘要
本文以矩陣分析設計法來實現差動差分電流傳輸器(Differential Difference Current Conveyor ；DDCC)和第二代完全差分電流傳輸器(Fully Differential second-generation Current Conveyor；FDCCII)為主動元件設計三階以及六階帶拒濾波電路其操作頻率為100kHz，並使用HSPICE配合TSMC 0.35µm製程參數進行電路模擬及分析。
本文以三階帶拒濾波電路模擬與分析為主，模擬的結果與理論值接近；由於六階帶拒濾波電路峰值不夠小，故本文針對六階帶拒濾波電路進行補償減少誤差。

關鍵字

差動差分電流傳輸器 ； 完全差分電流傳輸器 ； HSPICE ； 帶拒濾波器

並列摘要

Abstract
In this paper, using Matrix Analysis and Design Method to achieve differential difference current conveyor (DDCC) and a second-generation fully differential current conveyor (FDCCII) to be the active components designed for third-order and six-order band reject filter circuit whose operating frequency of 100kHz, and using HSPICE with TSMC 0.35μm process parameters to circuit simulation and analysis.
In this paper, the third-order band reject filter circuit simulation and analysis of the main simulation results with theoretical values close; due to the six-order band-reject filter circuit peak is not small enough, so this article for the six-order band-reject filter circuit to compensate for reducing errors.

並列關鍵字

HSPICE ； band reject filter ； FDCCII ； DDCC

參考文獻

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