低成本影像編碼轉換應用於高效能視訊編碼標準

Low-Cost Video Transform for HEVC

劉介揚(Chieh-Yang Liu)

指導教授 ： 陳元賀

中原大學/工學院/資訊工程研究所/碩士(2014年)

https://doi.org/10.6840/cycu201400840

摘要

在本篇論文中，我們提出了HEVC Inverse Transform硬體設計架構，可支援HEVC 4K(3840x2160)@30fps的畫質，並且可以針對不同的轉換單位(Transform unit, TU)尺寸32×32、16×16、8×8、4×4等進行運算。在製程技術的設計上，使用台積電90nm製程的技術製作Serial In -Serial Out多點(32×32、16×16、8×8、4×4) Inverse Transform核心，運算速度可以達到250MHz，而在0.18um的製程技術上針對32×32的Inverse Transform設計Parallel In-Parallel Out並提供兩條運算路徑的Inverse Transform核心，運算速度達到125MHz。兩顆設計均使用1組1-D IDCT運算核心搭配記憶體來完成2-D的Inverse Transform，實現硬體方面兩組Inverse Transform的實驗結果Throughput rate均在 250M pixels/s在gate count方面多點Inverse Transform包含記憶體與1-D Core 的gate count為110K gate，32點Inverse Transform則為84K。

關鍵字

影像編碼 ； 高效率影像編碼 ； 整數離散餘弦轉換 ； 離散餘弦反轉換

並列摘要

In this paper, we present a hardware design which can support for High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT) for 32×32 Transform Unit (TU) sizes is proposed and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform core which can calculate 1st-D and 2nd-D data simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 250-Mpels/s with 79k gate counts. Apart from that we have proposed a flexible architectures which could be used for implementing the IDCT of any of the prescribed lengths such as 4, 8, 16 and 32, each having particular advantage in terms of area, delay. The proposed architectures operating frequency is 250MHz. Furthermore, it can support Ultra-High-Definition (UHD) 3840 × 2160 @30fps video which is one of the applications of HEVC.

並列關鍵字

Video Coding ； High Efficiency Video Coding (HEVC) ； Integer DCT ； Inverse discrete cosine transform (IDCT)

參考文獻

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