考量矽穿孔數目之三維系統晶片的包裝鍊最佳化

系統晶片的設計由許多嵌入式的核心所組成，為了測試這些核心，模組化的包裝介面設計需要藉由串接包裝鍊元素形成數條包裝鍊，實現載入測試向量與卸載測試響應，而最長的包裝鍊將影響核心的測試時間，所以如何平衡包裝鍊的長度是ㄧ個重要的議題。隨著製程技術持續的微縮，連線長度變成一個不容忽視的問題，而三維晶片的提出為此帶來了解決辦法，但也為包裝介面設計帶來挑戰，因為包裝鍊元素在三維的架構中會散佈在不同層，所以我們不只需要平衡包裝鍊的長度還要同時降低TSV的使用數目，然而，過去的研究只用後續處理的方式來降低TSV的使用，因此會導致使用過多的TSV。基於我們的觀察，在這篇論文中我們針對包裝鍊最佳化的問題提出兩階段的演算法，不同於過去的研究，我們的目標是在TSV的限制下最小化測試時間。

關鍵字

三維系統晶片；矽穿孔；測試時間；包裝介面；包裝鍊

並列摘要

A system-on-Chip (SoC) design consists of many embedded cores. In order to test these embedded cores, modular wrapper design needs to connect scan elements to form test wrapper chains. Since the longest test wrapper chain affects the test time, how to balance these wrapper chains is an important topic. As the feature size continues to shrink, the wire length has become a serious concern. Three-dimensional integrated circuits (3D ICs) provides a promising solution, but it also brings a challenge in modular wrapper design. Since scan elements in a 3D IC spans multiple layers, we not only need to balance these wrapper chains but also need to reduce the number of through-silicon-vias (TSV) usages. However, previous work only uses a post-processing approach to reduce the TSV count. As a result, the previous work often leads to a large TSV count. Based on that observation, in this paper, we propose a two-stage algorithm for test wrapper chain optimization. Different from the previous work, our objective is to minimize the test time under the given TSV number constraint.

並列關鍵字

3D SoC, Through Silicon Vias ； Test Time ； Wrapper ； Wrapper Chain

參考文獻

[2] V. Iyengar, K. Chakrabarty and E. J. Marinissen, “Test Wrapper and Test Access Mechanism Co-optimization for System-on-chip”, Proc. of IEEE International Test Conference, pp. 1023-1032, 2001.

[3] E. J. Marinissen, et al., “Wrapper Design for Embedded Core Test”, Proc. of IEEE International Test Conference, pp. 911-920, 2000.

[4] D. Libao, B. Xiaolong, J. Chengyu and L. Yunchao, “Re-Optimization Algorithm for Wrapper Scan Chains Balance Based on Twice-Assigned Method Using Dynamic Adjustment and Mean Value”, Proc. of International Conference on Instrumentation and Measurement, Computer, Communication and Control, pp. 609-614, 2015.

[5] B. Noia, K. Chakrabarty and Y. Xie, “Test-wrapper Optimization for Embedded Cores in TSV-based Three-Dimensional SOCs”, Proc. of IEEE International Conference on Computer Design, pp. 70-77, 2009.

[6] Y. Cheng, L. Zhang, Y. Han, J. Liu and X. Li, “Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC”, Proc. of IEEE Asian Test Symposium, pp. 181-186, 2011.

國際替代計量

考量矽穿孔數目之三維系統晶片的包裝鍊最佳化

全文下載

主題瀏覽