應用於低電壓差分信號序列器／解序列器之鎖相迴路設計與實現

Design of a Charge-Pump PLL for LVDS SerDes

劉昱廷(Yu-Ting Liu)

指導教授 ： 陳淳杰

中原大學/電機資訊學院/電子工程研究所/碩士(2015年)

https://doi.org/10.6840/cycu201500522

摘要

本論文設計一個應用於低電壓差分信號(LVDS)序列器/解序列器(SerDes)之鎖相迴路(PLL) ，使用充電泵鎖相迴路，壓控震盪器選擇環形震盪器以節省電路面積。設計平台使用TSMC提供之 0.18 μm 1P6M CMOS 製程。在供應電壓為1.8V、輸入參考頻率為120MHz (輸出頻率為840MHz)的情況下，整體功率消耗為5.24mW，鎖定時間為12μs，輸出抖動為4.2ps。

關鍵字

鎖相迴路 ； 低電壓差分信號 ； 充電泵

並列摘要

In this paper, we design a PLL for low voltage differential signal(LVDS) serializer/deserializer. We can reduce the area of chip by using charge pump and ring oscillator. Design platform is 0.18μm 1P6M CMOS process. The output frequency is 840MHz at 120MHz input frequency. The power is 5.24mW at 1.8V power supply, setting time is 12μs and jitter is 4.2ps.

並列關鍵字

PLL ； LVDS ； Charge Pump

參考文獻

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