第四族半導體合金於先進奈米元件應變工程之分析與研究

Analysis and Investigation of Strain Engineering on Advanced Nanoscale Devices Using the Column IV Semiconductor Alloys

鄭森文(Sen-wen Cheng)

指導教授 ： 李昌駿

中原大學/工學院/機械工程研究所/碩士(2015年)

https://doi.org/10.6840/cycu201500858

摘要

近年來，由於金氧半場效應電晶體逐漸步入奈米尺寸世代發展，當電晶體之尺寸由32nm技術節點發展到16nm以下時，因微影與相關製程技術遭受嚴峻挑戰，致使應變工程之使用為目前一有效解決方法而在不微縮元件尺寸之同時而有效地增加元件工作效率。
本研究係利用有限單元分析，分別考慮金氧半場電晶體之源/汲極區域鑲埋矽鍺合金與矽碳合金等應變技術；操控兩個晶格間的晶格常數不匹配而引致晶格應力進而讓通道受到壓應力或是拉伸應力，藉此提升元件通道中之載子遷移率。同時，探討各種合金濃度對於通道引致應力大小；尤其當覆蓋具有應力之接觸蝕刻停止層的情況。分析結果指出當鍺濃度/碳濃度/錫濃度愈高，則因晶格不匹配程度愈大，故通道產生之壓縮/拉伸應力會益加明顯。為了讓本研究所使用之有限元素模擬分析具高信賴與準確性分析結果，亦與相關文獻進行驗證。驗證結果指出前述三種合金操控方法皆與文獻中實驗得到之數據相近，故本研究之有限元素模擬方法確實具有可行性。
此外，本研究中亦考慮元件佈局對於通道之應力分佈與效能之影響。研究指出，元件在源/汲極區域鑲埋矽鍺合金應力源，最大的電洞遷移率發生在無延伸閘極之處，其值約為65%，若元件使用25%之矽鍺合金應力源搭配-2.0GPa之接觸蝕刻停止層應力源，最大載子遷移率發生在延伸閘極寬度達到至150nm，其值為111.43%。在矽碳合金的研究指出，只鑲埋矽碳合金於源/汲極區域之應力源的條件下，最大電子遷移率為12.5%。然而，矽碳合金應力源搭配1.0GPa之接觸蝕刻停止層應力源，最大電子遷移率發生在延伸閘極愈短之處，其值於約55.2%左右。對於鍺錫合金而言，相同摻雜10%錫濃度之條件下，奈米元件之源/汲極區域長度達到700nm時，其電洞遷移率可高達121.6%。

關鍵字

應變工程 ； 有限元素分析 ； 接觸蝕刻停止層 ； 晶格應力

並列摘要

In recent years, the metal oxide semiconductor field effect transistor (MOSFET)　has gradually stepped into the nanometer-scaling generation. When the critical dimension of the transistor is scaled from 32nm to 16nm technology node and beyond, related process technologies, such as lithography, have sufferred a serious bottleneck. Consequently, the application of strained engineering becomes one of the effective solutions that can enhance the working efficiency of device components with the same structural framework.
This research used Finite Element Method (FEM) analysis to analyze the effect of strain engineering techniques including embedding silicon-Germanium (SiGe) alloy, Silicon-carbon (SiC) alloy, and germanium-tin (GeSn) alloy in the Source/Drain (S/D) region of MOSFET on device performances. In order to enhance the channel carrier mobility, manipulating lattice constants mismatch between SiGe/SiC/GeSn to cause either a compressive stress or a tensile stress with the region of device channel. In the meanwhile, investigating the channel stress differences by using different concentrations of various alloys is also implemented, especially for the condition of that a contact etch stop layer (CESL) is deposited. The analysis result indicates that the higher of the Germanium/Carbon/Tin concentration is, the degree of lattice constants mismatch will be higher. Thus, an increase of the compressive stress or tensile stress within the channel is more obvious. Morevoer, in order to acquire a highly reliable and precise result of FEM analysis, the proposed simulated methodology is also verified with related literatures. The analytic results with regard to the three manipulations of alloys shown in this research have a good agreement with the experimental data. In other words, the present simulated methodology proposed in this research is exactly feasible.
Furthermore, the layout pattern effect of nano-scaled transistors on stress contours and performances of the concerned short channel is also taken into account. The research result indicates that as device having embedded SiGe alloy stressor in the S/D regions, the maximum hole mobility of 65% occurs for the condition of that there has no extending gates. Combined with Si75Ge25 alloy stressors and a -2.0GPa CESL, it is found that a maximum hole mobility of 111.43% occurs at the exptended gate width up to 150nm. On the other hand, the analytic results regarding the adoption of S/D SiC alloys indicates that a maximum electron mobility up to 12.5% is achieved. As a tensile 1.0 GPa CESL is introduced, the mobility gain of about 55.2% occurs while the above-mentioned extending gate becomes shorter. For a GeSn stressor with the consideration of doping a 10% Sn concentration, manipulating the length of S/D region of nanodevice reaches a 700nm, the acquirement of a 121.6% in hole mobility could be realized.

並列關鍵字

Strain engineering ； Finite element method ； Contact etch stop layer ； Lattice stress

參考文獻

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