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  • 學位論文

採用交互二次取樣方法之電容式指紋晶片設計

Design of Capacitive Fingerprint Sensing Chip with Double Sampling Scheme

指導教授 : 許孟烈

摘要


近年來,指紋辨識應用在許多智慧手機上,其中最可靠的是電容式指紋感測器,電容式指紋感測器是藉由量測晶片的上層金屬與手指表面之間的電容來獲取指紋圖像,但手指的乾濕狀況和晶片表面的髒污會影響到電容的量測結果。所以本論文提出一種交互二次取樣方法的電路技術來實作電容式指紋感測晶片,以達到較高的輸出電壓範圍。 本論文採用TSMC 0.18um 1P6M CMOS標準製程實現一個16x16陣列的指紋感測器晶片,整體面積為898.715um × 1013.890um,工作電壓為1.8V,操作頻率為500kHz,解析度為500dpi,感測電容範圍為0fF~70fF,輸出電壓範圍為0.05V~1.28V。

並列摘要


In recent years, the capacitive fingerprint sensor chips have found many authentic applications in smart phone. The capacitive fingerprint sensor chip acquires the fingerprint image by measuring the capacitance between the top metal layer of the sensor chip and finger surface. However, the conditions of the finger and sensor chip surface may largely influence the capacitance measuring result. So, this thesis presents a capacitive fingerprint sensing chip with double sampling scheme to achieve a higher output voltage range. A fingerprint sensing chip with 16x16 sensor array is implemented in TSMC 0.18μm 1P6M standard CMOS process. The chip area is 898.715um x 1013.890um, works at 1.8V power supply, and operates at 1MHz. The fingerprint induced capacitance to be sensed ranges from 0 to 70fF, and the output voltage range is 0.02V-1.28V.

參考文獻


[1] Tractica針對生物辨識市場的預測與分析
https://www.tractica.com/newsroom/press-releases/global-biometrics-market-revenue-to-reach-15-1-billion-by-2025/
[2] 內政部警政署指紋八大類型-以右手為例
https://www.cib.gov.tw/Topic/Detail/1110
[3] 黃元展, 低寄生電容與低功率CMOS電容式指紋感測器之研製, 國立暨南國際大學電機工程學系碩士論文, 2007.

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