無摻雜雙閘極穿隧電晶體研究

Investigation of Doping-Less Double-Gate Tunnel Field Effect Transistors

王懷谷(Huai-Ku Wang)

指導教授 ： 施君興

國立暨南國際大學/科技學院/電機工程學系/碩士(2020年)

https://doi.org/10.6837/ncnu202000246

摘要

近年來，在傳統金氧半電晶體不斷微縮下，逐漸到達功耗與物理之極限，穿隧電晶體因可具有極小的次臨界擺幅及電晶體操作電壓，已成為未來綠能電晶體元件重要方向。其中，無摻雜穿隧電晶體的元件架構，具有無摻雜之通道特性，為可能發展方向之ㄧ。
此論文，利用二維模擬軟體，探討與分析無摻雜之雙閘極穿隧電晶體，利用適當的物理模型，研究主要元件結構和材料的關鍵參數變化，對於無摻雜穿隧電晶體其元件特性與穿隧機制之影響，進而尋求最佳化之元件設計及應用考量。

關鍵字

無摻雜 ； 穿隧電晶體 ； 二維元件模擬

並列摘要

Scaling traditional MOSFET transistors have results in severe power dissipation of integrated circuits. Tunnel field-effect transistor (TFET) has demonstrated its steep subthreshold swing to serve as a promising candidate for future energy-efficient devices. Recently, doping-less TFET was proposed to serve as an attractive approach. Using two-dimensional device simulations, this work investigates physical operations and device characteristics of doping-less TFETs. Various structures and device parameters were considered to optimize the doping-less TFETs for low-power, high-efficiency applications.

並列關鍵字

doping-less ； tunnel field effect transistor ； two dimensional simulation

參考文獻

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[2] A. C. Seabaugh and Q. Zhang, "Low-voltage tunnel transistors for beyond CMOS

logic," Proceedings of the IEEE, vol. 98, no. 12, pp. 2095-2110, 2010.