雙基底對數架構之數位訊號處理器晶片設計

The Chip Design of Dual Logarithm Based Digital Signal Processor

邱銘彰(ming-jhang ciou)

指導教授 ： 吳俊德

國立暨南國際大學/科技學院/電機工程學系/碩士(2008年)

https://doi.org/10.6837/NCNU.2008.00082

摘要

在本論文中，我們提出一顆可將資料做雙基底對數運算的數位信號處理器，利用其專屬的指令集將語音辨識演算法實現於數位信號處理器。使用硬體電路搭配軟體演算法整合設計的方式，來設計出最佳的電路架構以及專屬的特殊指令集。在電路架構設計方面，處理器具有雙基底對數運算的設計。若處理器中無對數運算的指令，在演算法中需使用對數運算，則必須利用其他方法來實現對數運算，因而費時且精準度不符要求，為此我們特地設計出一個具有對數運算能力的數位信號處理器，來快速處理演算法中的對數運算並且能得到較精確的結果。最後此晶片應用於TSMC 0.13um製程合成，其合成完成後的Gate count約為55萬，工作頻率最高約為50MHz。

關鍵字

數位訊號處理器,對數,晶片

並列摘要

In this study, we proposed a digital signal processor which supports dual logarithm based and use its specific instruction set to implement the speech recognition algorithm. We use hardware-software co-design methodology to optimize the processor architecture and instruction set. In terms of architecture, the processor supports dual logarithm based operator. If the processor doesn’t support logarithm operator, we must use other method instead logarithm operator when using it. But it cost a lot of time and its resolution is not enough precise to we need. So we design a processor which supports logarithm operator to evaluate logarithm quickly and get more precise resolution. Finally, the total gate count of this processor is about 550,000 synthesized and estimated with TSMC 0.13 um standard library. The maximum clock frequency of this processor is about 50MHz.

並列關鍵字

DSP,Logarithm,CHIP

參考文獻

[1] Frank Vahid, Tony Givargis, Embedded System Design: A Unified Hardware/Software Introduction, John Wiley & Sons Inc, 2002.

[2] Baumhof C, Muller F, Muller O, Shlett M, “A novel 32 bit RISC architecture unifying RISC and DSP” Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on Volume 1, 21-24 April 1997 Page(s):587 - 590 vol.1

[3] Dolle M, Jhand S, Lehner W, Muller O, Schlett, M, “A 32-b RISC/DSP microprocessor with reduced complexity” Solid-State Circuits, IEEE Journal of Volume 32, Issue 7, July 1997 Page(s):1056 - 1066

[4] Hassler, H.; Takagi, N.; ” Function evaluation by table look-up and addition” Computer Arithmetic, 1995., Proceedings of the 12th Symposium on 19-21 July 1995 Page(s):10 - 16 Digital Object Identifier 10.1109/ARITH.1995.465382.

[5] Yi Wan; Chin-Long Wey; ” Efficient algorithms for binary logarithmic conversion and addition” Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Volume 5, 31 May-3 June 1998 Page(s):233 - 236 vol.5 Digital Object Identifier 10.1109/ISCAS.1998.694452