由於先進互補式金氧半導體製程技術採用更低的電源供應電壓,導致元件的特性較以往退化。在奈米尺度的製程中使用類比方式設計一個高解析度的類比數位轉換器將越來越困難。然而,另一個克服低電壓且高解析度類比數位轉換器設計挑戰的方法便是轉而用時域來表現訊號。 本論文所提出一個八位元以循環式時間數位轉換器為基礎的類比數位轉換器。當中有多個關鍵的設計技術。首先是循環式的時間數位轉換器,其非但保有高解析度並且也進一步擴展輸入動態範圍。次之是單次的校正演算法,與傳統循環式的時間數位轉換式相比較,本論文所提的方法不需要複雜的校正程序和晶片外昂貴的專用設備。值得一提的是為了滿足不同的應用需求,單次校正功能也可以用來設定類比數位轉換器的輸入動態範圍及/或解析度。 根據上述的架構與技術,我們實現了一個操作於1.8伏特的八位元循環式類比數位轉換器。當使用TSMC 0.18-μm 1P6M CMOS製程時,模擬結果顯示電路取樣速率可達2MS/s且電壓解析度為0.49mV。同時,DNL和INL分別介於-0.5/+0.25LSB和-0.75/+0.75LSB之間且ENOB為7.69 bits。整體電路功率消耗約為1.45mW。
Advanced CMOS process technology adopts a lower power supply voltage that results degraded device characteristics. Using analog approach to design a high-resolution analog-to-digital converter (ADC) in nanoscale processes is more and more difficult. However, an alternative way to overcome the design challenges of low-voltage and high-resolution ADC is to represent signals in the time domain. In this thesis, an 8-bit ADC based on a cyclic time-to-digital converter (TDC) is proposed. There are many significant design techniques with this proposed ADC. The first is a cyclic TDC that keeps the resolution as high as possible as well as enlarges the input dynamic range. The second is a one-shot calibration algorithm that removes not only the complicated correction procedure but also the expensive off-chip dedicated equipment, compared to conventional cyclic TDC’s. It is worth to mention that one-shot calibration feature can also be used to set the input dynamic range and/or resolution of the proposed ADC for different applications. Based on the proposed architecture and techniques, a 1.8V 8-bit ADC is realized. The converter is simulated by the TSMC 1P6M 0.18μm CMOS process, the results show that the ADC achieves a 2MS/s sampling rate and the resolution is 0.49mV. Meanwhile, the DNL and the INL of the proposed ADC are within -0.5/+0.25LSB and -0.75/+0.75LSB, respectively and the ENOB is 7.69 bits. The power consumption is 1.45mW.