高-K值介質HfSiON及HfAlON在低溫下之C-V、I-V及應力後之行為

本論文旨在利用電容-電壓(C-V)、電流-電壓(I-V)的量測技術來對目前被研究學者所看好的HfSiON及HfAlON高-k值介質材料進行低溫環境下的特性研究，期望瞭解在不同溫度下是否會對遲滯、介面電荷或是電流之現象產生影響；另一方面，可靠度的研究可說是材料能否應用在元件上重要的一環，因此我們也將對此兩種介電層分別施加不同時間之定電壓應力及定電流應力，分析並比較其應力作用前後特性的變化。由實驗結果，我們發現當在低溫下對HfSiON及HfAlON介電層進行頻率100kHz或1MHz之電容-電壓量測時，聚集區電容皆出現隨著溫度的增加而減少的趨勢，且低溫下之頻率散射現象較高溫來的小許多。為了探究此問題，我們藉由three-element model及four-element model進行C-V特性的修正來得出介電層實際的電容-電壓曲線，而從模擬出的曲線我們認為使用four element model能得到較佳的結果。另外，從C-V遲滯曲線之量測，我們可以發現兩種介電層材料呈現遲滯方向相反的趨勢，我們認為這是因為HfAlON的缺陷較靠近介面層而HfSiON缺陷則較接近金屬閘極所導致的。隨後，我們利用此修正之電容-電壓曲線進行遲滯的計算，發現遲滯現象隨著溫度的增加而增加，這是因為當溫度增加時，環境熱能提供給介電層缺陷的能量跟著增加而使其補陷機率增高，因此遲滯的現象越明顯。而溫度降低時環境熱能提供的能量也跟著減少，所以補陷機率降低，故而遲滯量隨溫度上升而增加。另外，在介面電荷密度方面，我們發現介面電荷密度是隨著溫度的增加而減少的，這是因為較高溫時產生的電子-電動對來填補介面缺陷所造成的影響。而在電流-電壓曲線方面，我們經由量測發現無論在正、負閘極電壓下，電流皆隨著溫度增加而增加。經由分析發現，在負閘極電壓VG= -1V、VG= -1.25V、VG= -1. 5V下，高介質中之電流在溫度大於150K時為Frenkel-Pool傳導，而小於150K則為Ionic Conduction的傳導機制。再者，我們也對樣品施加不同時間之定電壓應力及定電流應力，我們發現在負定電壓應力作用下，平帶電壓VFB位移皆隨應力增加而增加，且負電壓應力相對比正電壓應力所造成的VFB位移要來的大，這是因為相對注入較多的電荷到氧化層所造成的結果。而藉由施加應力之遲滯比較，我們可以確認HfSiON介電層比起HfAlON介電層有著小許多的遲滯表現，故而是未來金氧半元件應用的較佳選擇。

關鍵字

高k質介質；低溫特性； C-V ； I-V ；定電壓應力及定電流應力

並列摘要

The main purpose of this thesis is to study the low-temperature behaviors of two most promising high-k dielectrics, HfSiON and HfAlON, by measuring their capacitance-voltage (C-V) and current-voltage (I-V) characteristics at low temperatures, such that we can understand the effects of different temperatures on the hysteresis, interface charge density and the leakage current in the high-k dielectrics. On the other hand, reliability study is one important technique to determine whether a dielectric can be used as the gate material in metal-oxide-semiconductor (MOS) devices. Therefore, we also applied constant voltage stress and constant current stress with different time extends to explore the difference between the pre- and post-stress characteristics of the two high-k materials. From our experimental results of 100 kHz and 1 MHz C-V characteristics measured at low temperature, we found that the capacitance in accumulation region reduces with increasing temperature and the frequency dispersion phenomenon at low temperature is smaller than that at high temperature. In order to find out the root cause and to obtain more accurate C-V curves, we used the three-element as well as four-element models to modify the measured C-V curves. Based on our calculation results, we believed that the use four-element model can fit the C-V curves more accurately. We also observed that the two high-k dielectrics exhibited opposite direction in their C-V hysteresis curves. A possible explanation for this is that the HfSiON has oxide traps that are closer to the metal/oxide interface, while HfAlON has traps locate near the oxide/Si interface. From the modified C-V curves we also obtained the hysteresis voltage difference, which showed an increase in hysteresis voltage difference as the temperature increases. This is because that, with increasing temperature, higher thermal energy produces more electron-hole pairs so that the probability of those carriers being trapped is increased. When the temperature is reduced, the decrease of thermal energy produces less electron-hole pairs that give less probability of being trapped. For interface-trap-density, we found that it reduces with increasing temperature. We inferred the reason for this is that more electron-hole pairs produced at the higher temperature are filled in the interface traps. For the I-V curves, we found that the gate leakage current increases with increasing temperature for either positive or negative gate voltage. By fitting those I-V curves at gate voltages VG = -1 V, VG = -1.25 V, and VG = -1.5 V, we found that it obeys the Frenkel-Pool conduction when the temperature is greater than 150K, while it is ionic conduction when the temperature is smaller than 150K. Constant voltage stress and constant current stress with different time extends were applied to the two high-k samples, we found that the stress-induced flat-band voltage shift VFB increases with increasing stress voltage or stress current when gate is biased negatively. Much more VFB shifts were observed when negative constant voltage was applied to the samples because more electrons were injected into the oxides when gate is biased negatively. The post-stress hysteresis of HfSiON electricity layer is much less than that of HfAlON high-k dielectric. Therefore, we conclude that HfSiON high-k dielectric is a better candidate for future application in MOS devices.