K-頻帶CMOS鎖相迴路相關電路方塊之設計及實現

Design and Implementation of CMOS K-Band Phase-Locked Loop Related Circuit Blocks

張富傑(Fu-Chieh Chang)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2008年)

https://doi.org/10.6837/NCNU.2008.00181

摘要

本論文設計一個應用在汽車自動防撞系統（automatic bump-shielded system of the automobile）的24GHz之鎖相迴路，使用LC共振腔之振盪器與Mixer除頻器。此論文有六個章節，第一章為對此鎖相迴路之功能及應用上做簡略性的介紹。
第二章為鎖相迴路之基本原理的介紹。
第三章為介紹壓控振盪器的設計考量，壓控振盪器為此論文專題中最高頻段部分，也是整個系統最具挑戰性的部分，且用TSMC 0.18μm技術實現K頻段壓控震盪器。
第四章介紹Mixer除頻器之原理與設計考量，利用Mixer的概念設計之除頻器其有較寬之可除頻頻寬。首先使用TSMC 0.18μm技術實現一Ka頻段Mixer除頻器，鎖定頻寬為3.6GHz(11.726% )，從28.9GHz到32.5GHz，消耗功率為25.884mW，在1.8V的偏壓下與14.38mA核心電流；最後設計一個K頻段Mixer除頻器並使用在K 頻段之鎖相迴路。
第五章介紹鎖相迴路之基本原理與各個方塊。首先我們實現鎖相迴路中之壓控震盪器、Mixer除頻器和數位部份的CML除頻器。最後完成鎖相迴路，其鎖定時間約為10us。

關鍵字

壓控震盪器,Mixer除頻器,鎖相迴路

並列摘要

This thesis designs a 24GHz Phase-Locked Loop (PLL) of automatic bump-shielded system of the automobile, using LC tank Voltage-Controlled Oscillator (VCO) and Mixer divider. The thesis has six chapters. The first one is simple introduction to capability and application of the PLL.
The second chapter explains the basic of PLL
The third chapter explains the principle of VCO. VCO is not only the highest frequency in the thesis but the most challenging part in the system. Therefore we can use TSMC0.18μm to achieve K-Band VCO.
The forth chapter shows the principle and design Mixer divider. It has wider locking range. First TSMC0.18μm finishes a ka band Mixer divider. The bandwidth is 3.6GHz (11.726%) from 28.9GHz to 32.5GHz. The power consume is 25.884mW on condition that core current is 14.38mA and bias is 1.8V. Finally, designing a k band Mixer divider and applied to k band PLL.
The fifth chapter tells about the principle and block in PLL. First of all we achieve VCO、Mixer divider and CML at PLL. Lastly PLL is complete, it locking time at 10us.

並列關鍵字

Voltage-Controlled Oscillator,Mixer Divider,Phase-Locked Loop

參考文獻

[1] ”RF Microelectronics” PRENTICE HALL PTR, 1998 Behzad Razavi

[2] A. Hajimiri and T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” Solid-State Circuits, IEEE Journal of Volume 33, Issue 2, Feb. 1998 Page(s):179 – 194.

[3] B. De Muer, M. Borremans, M. Steyaert, and G. Li Puma, “A 2-GHz Low-Phase-Noise Integrated LC-VCO Set with Flicker-Noise Upconversion Minimization,” Solid-State Circuits, IEEE Journal of Volume 35, Issue 7, July 2000 Page(s):1034 – 1038.

[4] Behzad Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill International Edition,20001

[5] 高曜煌”射頻鎖相迴路IC設計”