基於延遲鎖定迴路之倍頻器的FPGA設計與實現

隨著製程的演進，積體電路朝向高速、高密度整合的系統單晶片發展。為系統單晶片提供一個穩定、低時脈抖動且具抗製程、溫度、電壓影響的內部時脈訊號變成日趨重要的研究主題。近年來，現場可規劃邏輯閘陣列(Field Programmable Gate Array , FPGA)的容量及效能上皆有長足的提升。越來越多的電路設計者利用此設計容易且低成本的平台來量產或驗證自行設計的系統單晶片。在FPGA實現中，設計者因邏輯化簡與繞線佈局等軟體限制而使設計自由度降低，因此傳統在FPGA中系統單晶片的時脈產生器自行設計不易。本論文運用FPGA晶片中查找表與進位鏈的特性，發展了三種設計方法。以基於延遲鎖定迴路之倍頻器架構與上述的設計方法，自行設計的時脈產生器已透過硬體描述語言成功實現於FPGA中。實驗結果證實，本論文所提出的倍頻器於Altera DE2-70 FPGA實驗板實現時，其最高倍頻輸出可達480MHz且輸入頻率範圍為33MHz到120MHz。

關鍵字

現場可規劃邏輯閘陣列(FPGA) ；延遲鎖定迴路；倍頻電路

並列摘要

With the evolution of process technology, the development of the integrated circuit has moved toward a high-speed and high-integrated System-on-a-chip (SoC). Providing the SoC clock signals with properties of low timing jitter and PVT-immunity has become more and more important research topics in these few years. In recent years, the capacity and performance of Field Programmable Logic Gate Array (FPGAs) have increased drastically. More and more circuit designers nowadays utilize such low cost FPGA platforms to design and verify their own SoCs and even go into mass production. However, in the FPGA development cycle, the Electronic Design Automation (EDA) tool sometimes becomes an issue due to its logic optimization and placement and routing (P&R) that will correspondingly decrease the freedom for the circuit designers. Therefore, it is difficult to implement add-on clock generating circuits on FPGAs. We characterized both the properties of carry chain and look-up table (LUT) of FPGA to develop three types of design methods in order to solve logic optimization and P&R related issues caused by EDA tool. By using those proposed design methods and through the Verilog Hardware Description Language (Verilog HDL), we succeeded in implement the delay-locked loop based frequency multiplier circuit on the FPGA. After prototyping the whole system on Altera DE2-70 FPGA development board, the experimental results confirm that the maximum output frequency of the proposed frequency multiplier reached up to 480MHz and the acceptable input frequency ranges from 33MHz to 120MHz.