低功率超寬頻低雜訊放大器之設計與實現

Design and Implementation of Low-Power Ultra-Wideband Low Noise Amplifier

吳家興(Chia-Hsing Wu)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2011年)

摘要

本論文以低功率、超寬頻(Ultra-wideband)低雜訊放大器為研究目標，研究主題分成三部分：

第一部份為應用於接收機超寬頻系統之低功率3.1~10.6 GHz低雜訊放大器。利用電流共用技術設計了兩組低功率的CMOS低雜訊放大器，為了同時達到高且平坦的增益及較小的群延遲變化，在輸出級分別採用了串、並聯電感補償技術來增加主極點頻率，進而擴展3 dB頻寬。輸入級部份則使用電阻-電容負回授來達成匹配，並且有效的縮小電路面積。
首先，我們利用0.18 mm CMOS製程設計了第一組低雜訊放大器，並使用電流共用技術和串聯補償電感來做探討。實驗結果顯示低雜訊放大器在3.1~10.6 GHz頻率下有著平坦增益S21為12.52 ± 0.8 dB，輸入返回損耗低於-10.2 dB，輸出返回損耗低於 -7.3 dB，出色平坦的雜訊指數2.87±0.19 dB，以及群延遲變化為15.79 ps，此電路消耗之功率為11.808 mW。為了達到更好的特性，例如超低功率損耗。除了使用第一組架構，第二組低雜訊放大器還使用了self-forward-body-bias (SFBB)技術以及forward-combining技術達到足夠的增益、低雜訊以及超低功率的特性。實驗結果顯示低雜訊放大器在3.1~10.6 GHz頻率下有著平坦增益S21為10.92 ± 0.92 dB，輸入返回損耗及輸出返回損耗皆低於 -10 dB，以及雜訊指數3.04~3.69 dB，此電路消耗之功率為2.097 mW。非常適合應用在高解析度的脈波超寬頻系統。
第二部份為一可應用於汽車雷達系統的21~26 GHz超寬頻低雜訊放大器，利用台積電0.18 mm CMOS 製程技術來實現。仍然利用電流共用技術設計了兩組低功率的CMOS低雜訊放大器。首先我們設計第一組低雜訊放大器為三級串接共源級放大器，在第二級和第三級使用電流共用技術降低電流，並使用inductive peaking技術增加頻寬。第一組實驗結果顯示低雜訊放大器在21~26 GHz頻率下有著3-dB頻寬為9.5 GHz，平坦增益S21為9.61 ± 0.83 dB，輸入返回損耗低於-9.2 dB，輸出返回損耗低於 -5.3 dB，雜訊指數4.9~5.5 dB，以及群延遲變化為15.3 ps，此電路消耗之功率為10.84 mW。為了達到超低功率損耗，除了使用第一組架構，第二組低雜訊放大器還使用了self-forward-body-bias (SFBB)技術達到足夠的增益及低功率的特性。實驗結果顯示低雜訊放大器在21~26 GHz頻率下有著平坦增益S21為11 ± 0.77 dB，輸入返回損耗及輸出返回損耗皆低於 -10 dB，以及雜訊指數3.85~4 dB，此電路消耗之功率為2.8875 mW。非常適合應用於需要高解析度的雷達系統。
最後，我們利用台積電90 奈米 CMOS 製程技術設計一超寬頻、低功率V頻低雜訊放大器。為了達到足夠的增益和低功率損耗，我們利用四級串接共源級放大器和inductive peaking技術並使用了self-forward-body-bias (SFBB)技術來設計低雜訊放大器，在第二級和第三級採用了電流共用技術來降低功率的消耗。實驗結果顯示低雜訊放大器在50~64 GHz輸入返回損耗低於-10.8 dB，輸出返回損耗低於 -10.68 dB，增益S21為11.95 ± 1.37 dB，雜訊指數為6.04~6.46 dB。3-dB 頻寬為18.8 GHz (45.6~64.4 GHz)。這個低雜訊放大器有非常低6.87mW的功率消耗，非常適合整合於V頻帶的前端接收機中。

關鍵字

低雜訊放大器 ； 超寬頻 ； 低功率 ； 24 GHz短距離汽車防撞雷達 ； V頻帶低雜訊放大器 ； 電流共用 ； 電感補償

並列摘要

This thesis aim is to design low-power ultra wideband low noise amplifiers. Study the theme can be divided into three parts：
In the first part, 3.1-10.6 GHz low-power low-noise amplifier is designed for ultra wideband. The mainly two types of low noise amplifier were using current-sharing technique to achieve low-power consumption. In order to achieve not only high but also flat gain and small group-delay-variation at the same time, the series and shunt inductive peaking were adopted in the output stage to enhance the frequency of the dominant pole and then expand 3-dB bandwidth of the LNA. In the part of input stage, the R-C negative feedback can achieve impedance matching and reduce chip area.
At first, we design the first type of LNA in standard 0.18 ?m CMOS technology and employed current-sharing technique and inductive peaking. The measured results of the first type LNA show flat S21 of 12.52 ± 0.8 dB, S11 below -10.2 dB, S22 below -7.53 dB, excellent flat noise figure of 2.87±0.19 dB, and the group delay variation only ±15.79 ps over 3.1 to 10.6 GHz while consuming 11.808 mW. In order to pursue better performances such as ultra low-power consumption. In addition to the first type LNA architecture, the second type of LNA employed the self-forward-body-bias (SFBB) technique and forward-combining technique to achieve sufficient gain, lower NF and ultra low-power consumption performance. The simulated results of the second type LNA show that the flat power gain (S21) of 10.92 ± 0.92 dB, input return loss (S11) and output return loss (S22) below -10 dB, noise figure of 3.04~3.69 dB over 3.1 to 10.6 GHz while consuming 2.097 mW. These results show that the LNAs are suitable for UWB pulse-radio system applications.
In the second part, 21~26 GHz low-power low-noise amplifier is implemented in standard TSMC 0.18 ?m CMOS technology and suitable for radar system. The mainly two types of low noise amplifier were still using current-sharing technique to achieve low-power consumption. At first, we design the first type of LNA is composed of three cascaded common-source stages. The current-sharing technique with inductive peaking is adopted for bandwidth enhancement and in the second and third stage. The measured results of the first type LNA show that the 3dB bandwidth is 9.5 GHz, the flat S21 of 9.61 ± 0.83 dB, S11 below -9.2 dB, S22 below -5.1 dB, noise figure of 4.9~5.5 dB, and good group-delay-variation (±15.3 ps) over 21-26 GHz while consuming 10.84 mW. In order to pursue ultra low-power consumption. In addition to the first type LNA architecture, the second type of LNA employed the self-forward-body-bias (SFBB) technique to achieve sufficient gain and low-power consumption performance. The simulated results of the second type LNA show that the S21 of 11 ± 0.77 dB, S11 and S22 below -10 dB, noise figure of 3.85~4 dB over 21-26 GHz while consuming 2.8875 mW. These results show that the LNAs are suitable for high resolution radar systems.
Finally, we design a low-power V-band UWB LNA in TSMC 90 nm CMOS technology. In order to achieve sufficient gain and low-power consumption, this LNA is composed of four cascaded common-source stages, inductive peaking, and employed self-forward-body-bias (SFBB) technique. Current-sharing technique is adopted in the second and third stage to reduce the power dissipation. The simulated results show S11 of –10.8 dB, S22 of –10.68 dB, and S12 of –40 dB, S21 of 11.95 ± 1.37 dB, NF of 6.04-6.46 dB were achieved at 50-64 GHz. The 3-dB bandwidth of AV was 18.8 GHz (45.6-64.4 GHz). This LNA consumed only a small dc power of 6.87 mW. According to the performance, very suitable conformity in V-band front end receiver.

並列關鍵字

low noise amplifier ； ultra wideband ； low power ； 24-GHz short-range radar system ； V-band low noise amplifier ； current-reuse ； inductive peaking ； self forward body bias (SFBB) ； forward combining

參考文獻

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