精簡型延遲重複利用的時脈扭曲補償及/或工作週期矯正電路

A Compact Delay-Recycled Clock Skew-Compensation And/Or Duty-Cycle-Correction Circuit

游仁宗(Jen-Tsung Yu)

指導教授 ： 王義明

國立暨南國際大學/科技學院/電機工程學系/碩士(2011年)

https://doi.org/10.6837/NCNU.2011.00253

摘要

時脈扭曲補償及/或工作週期矯正器常運用於雙緣觸發時脈同步系統中，有助於協助其效能之提升。傳統的時脈扭曲補償及/或工作週期矯正器之架構大多都採用直接串接之型式，此種做法衍生出不少的問題。其一為冗長的鎖定程序將導致整體電路之效能下降；其二為雙迴路之設計使得硬體複雜度增加。
本論文提出一個延遲重複利用的時脈扭曲補償及/或工作週期矯正電路，其具有兩個關鍵的設計觀念；首先是快速鎖定與低功率的量測-調整架構。次之為頻寬增廣技術。
綜合上述各項技術並相較於傳統的CSADCs電路，本電路在功率消耗方面約下降了4.24倍，在功率頻寬比上約下降了7.93倍，而在鎖定時間方面約可減少1.11倍。在TSMC 0.18-μm CMOS製程、操作電壓為1.8V時，HSPICE電路模擬結果顯示電路可操作輸入訊號頻率範圍為300MHz - 2GHz，且矯正後之輸出訊號工作週期變異範圍為48.41% - 55.51%。當系統操作於2GHz時，可接受之輸入工作週期範圍為30% - 70%，鎖定後最大相位誤差為67ps，功率消耗僅5.87mW。

關鍵字

系統單晶片 ； 工作週期矯正器 ； 工作週期失真 ； 時脈錯離

並列摘要

A clock skew-compensation and/or duty-cycle correction circuit (CSADC) is indispensably required to maximize the performance of a synchronous double edge clocking system. Most conventional CSADC adopted a cascade structure that inherits a lower performance property that is causing a slower the locking procedure, meanwhile the dual loop design results in more design complexity.
In this thesis, a compact delay-recycled CSADC was proposed. There are two significant design concepts in the CSADC. The first is a fast locking and low power measure-and-tuned architecture. The second is a bandwidth augmentation technique.
Compared to conventional CSADCs, the proposed circuit achieves at least a 4.24 times reduction in power, a 7.93 times reduction in power bandwidth ratio, and a 1.11 times reduction in lock-in cycles. In TSMC 0.18-μm 1P6M 1.8V CMOS process, the “input signal frequency range” of the proposed CSADC from 300MHz to 2GHz, and the corrected duty cycle variation ranges from 48.41% to 55.51% are confirmed through HSPICE circuit simulation. When the clock frequency is 2GHz, the acceptable input duty cycles ranges from 30% to 70%. Besides, the aligned phase error and power consumption are 67ps and 5.87mW, respectively.

並列關鍵字

Soc ； duty-cycle corrector ； duty cycle distortion ； clock skew

參考文獻

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