新穎型焦平面感測陣列讀取電路積體化設計與系統實現之研究

Study on Design and Implementation of Novel Readout Integrated Circuit and System for Focal Plane Array Sensors

呂藝全(Yi-Chuan Lu)

指導教授 ： 孫台平

國立暨南國際大學/科技學院/電機工程學系/博士(2014年)

https://doi.org/10.6837/NCNU.2014.00291

摘要

紅外線焦平面陣列(Focal Plane Array, FPA)讀取電路是扮演紅外線感測器及後端系統溝通介面，讀取電路性能影響著影像品質，其重要關鍵技術在於像素電路設計，然而，像素微小化是提升影像解析度重點之一，因此，陣列式讀取電路將著重於像素電路。
近年來，為了提升感測器的偵測範圍、靈敏度、解析度，雙波段感測器漸漸成為重點研究項目，相對的，其所搭配陣列讀取電路設計關鍵技術需追隨感測器特性，回顧過去紅外線陣列讀取電路的研究文獻，像素電路設計主要採用DI、BDI、CTIA三大類型，然而，讀取電路設計依據於感測器特性，設計不同電路結構實現像素電路設計概念與可行性。因此，本論文針對雙波段感測器提出四種新穎式讀取電路設計，透過國家晶片設計中心，採用TSMC 0.35um 2P4M 5V製程進行設計、模擬、實做，晶片陣列大小10 x 8，時脈主頻3MHz下設計不同類型電路，晶片量測與測試分析相關規格說明於本論文內。
本論文提出一個單級主動負載放大器作為轉阻放大器架構，並以開關切換模式調控制兩種感測測器P-N-P與N-P-N。為了改善傳統BDI與CTIA於單一像素內面積過大問題，本論文提出利用佈局面積分享方式，可減少它一半面積與功率消耗，利用DI、BDI、CTIA三種不同電路結構設計，能選擇兩種不同讀取電路架構，提升陣列讀取電路功能與性能。當感測器光電流或暗電流訊號較強時，能夠選擇不同積分電容值，本論文提出以電容分享方式設計積分電容可調模式，提升整體感測訊號雜訊比。
本文將所設計讀取電路晶片連接後端影像系統，完成影像輸出與顯示，然而，訊號介面電路扮演重要角色在類比訊號至數位訊號之間，故訊號介面電路設計涉及整體影響速度與品質，並搭配讀取晶片驗證結果，整體系統解析度達到10 bit，像素輸出操作速度為1.47MHz，整體系統類比數位轉換時間為681ns，灰階解析度為1024。

關鍵字

雙波段 ； 雙切換 ； 讀取電路 ； 像素電路 ； 晶片 ； 陣列

並列摘要

A focal plane array (Focal Plane Array, FPA) readout integrated circuit plays an important role in both infrared detector and backend system communication interface. The performance of integrated readout system has a significant effect on image quality. Thus, the key technology to enhance image quality relies on the pixel circuit design. The pixel miniaturization is one of the key technologies to upgrade image resolution. Therefore, array readout integrated circuit will focus on the pixel circuit design.
In order to improve detection range, sensitivity and resolution, dual-band sensors have become the focus of the most recent research. Thus, readout circuit design should be in line with the characteristics of the latest sensor technology. Reviews of the past literature concerning ROIC, the DI, BDI and CTIA show these to be the three main pixel circuit architectures currently in use. In accordance with the characteristics of the latest sensors, different pixel circuit designs must be structured to achieve circuit feasibility. This thesis proposes four unique types of read circuit style dual-band sensors. The readout circuit is designed, simulated and implemented using a TSMC 0.35um 2P4M 5V process from the National Chip Implementation Center (CIC). The array size of the chip is 10x8 and the ROIC operates at a maximum clock frequency of 3MHz. The measured specification and analysis of the chip is explained in the thesis.
This thesis proposes a single-stage amplifier for use as an active load trans-impedance amplifier architecture with two sensors, PNP and NPN, controlled by the switch. It is comparable to conventional differentials in order to reduce the amplifier area. To improve the amplifier area and power consumption of the traditional BDI and CTIA unit pixels, this thesis proposes a layout area sharing method to reduce the area and power consumption by one half. The use of DI, BDI, and CTIA allows the design of three different pixel circuits. It chooses between two different structures to enhance functionality and performance. When the induced current is large or when the dark current is strong, capacitance can be adjusted. This thesis also proposes a capacitor-sharing method for ROIC in order to enhance the signal to noise ratio of integrated sensing.
The designed ROIC connects a back-end imaging system to complete the output and display. However, the proxy board circuit plays an important role in converting analog signals to digital form; the design of the proxy board circuit affects the overall impact of speed and quality. The readout chip connects to a proxy circuit board and display board to produce a grayscale image with a readout resolution of 10 bits and a pixel output speed of 1.47 MHz. The overall time required for analog to digital conversion was 681ns. The color gray scale was 1024.

並列關鍵字

Dual Band ； Dual Switch ； Readout Circuit ； Pixel Circuit ； Chip ； Arrays

參考文獻

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