垂直式氧化銦鎵鋅薄膜電晶體之研究

Study on Vertical Indium-Gallium-Zinc Oxide Thin-Film Transistors

陳俊源(Chun-Yuan Chen)

指導教授 ： 陳建亨

國立暨南國際大學/科技學院/電機工程學系/碩士(2019年)

摘要

本論文研究垂直式氧化銦鎵鋅薄膜電晶體，進行理論探討、元件設計、製作與量測。不同於一般垂直結構，設計出多個通道及雙邊閘極結構，改善電晶體效能；使用鉬金屬製作元件各電極，並利用濺鍍方式沉積氧化銦鎵鋅作為元件主動層，在整體氣體流量不變的情況下調整氧流量至3%和5%，並對薄膜進行分析，且沉積25至100nm的氧化銦鎵鋅薄膜探討對元件電性之影響，也改變製程順序製作兩種結構降低元件寄生電容的產生。
經過霍爾量測，氧化銦鎵鋅薄膜載子濃度為7.34×1015至1.32×1018cm-3；鍍膜經過250℃退火表面粗糙度為(RMS) 6.454nm；也使用SEM量測元件剖面圖，成功製作出top-contact多通道垂直薄膜電晶體。

關鍵字

垂直式薄膜電晶體 ； 氧化銦鎵鋅

並列摘要

In this work, we study on the fabrication of vertical indium-gallium-zinc oxide thin-film transistors. A multi-channel vertical IGZO TFTs were designed and fabricated. The metal Mo layers was sputtered as electrode and IGZO thin film active layer was deposited by pulsed-DC sputter. The IGZO thin film was deposited in 3% and 5% oxygen/argon mixed gas flow. The thickness of IGZO were about ~25-100nm. Then the devices were fabricated with two different structure to reduce the terminal parasitic capacitance.
With Hall effect measurement, the carrier concentration of IGZO thin film are about ~7.34×1015-1.32×1018cm-3. The thin film surface roughness was about ~6.454nm for the samples that annealing at 250℃. The cross-section of vertical TFTs were studied by SEM. The top-contact multi-channel vertical TFTs were fabricated successfully.

並列關鍵字

Vertical Thin-Film Transistors ； IGZO

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