摘要
當半導體元件微縮至深次微米之?域時，?氧半場效電晶體具環繞閘極結構能有效?低短通道效應且具備?想之次?界斜?。短通道效應使得元件應用?位電?時，產生?電?導致?必要之功?消耗，進而影響電?的功能。因此研究矽?米線場效電晶體元件元件成為刻?容緩之事。 本?文研究?用已經發展成熟的矽半導體製程技術，與熱氧化應?限制原?，設計製作完全環繞式閘極之矽?米線場效電晶體元件。本研究之矽?米線場效電晶體，其?米線定義範圍為直徑20?50?米、長?200?400?米。於室溫下?測其元件特性，發現其電性除完美呈現出標準場效電晶體之特性外，於某些元件中?呈現出庫?阻斷現象之特性。我們推測形成電?-電壓特性圖呈現階梯現象之原因，乃為絕緣層上之矽元件層進?摻雜製程時，恰巧於通道中形成砷島所造成。本研究結果成功?用熱氧化應?限制原?製作出直徑50?米以下之矽?米線。
並列摘要
As semiconductor devices are scaled into to the deep submicron meter regime, surrounding-gated silicon on insulator metal-oxide-semiconductor field effect transistors have shown promise in both the short-channel effect and in achieving a nearly ideal subthreshold slope. To control the surrounding-gated SOI MOSFET’s very well, when they are applied to the VLSI, there is a need to develop an accurate model for the suspended silicon nanowire field effect transistors. In this study, we use the well developed silicon semiconductor process and the Stress Limited Oxidation to fabricate fully-surround gated silicon nanowire field effect transistor. The present SiNW-FET had dimensions of 20 ~ 50 nm in diameter and 200 ~ 400 nm in length, and exhibited well pronounced classical field effect transistor characteristics and Coulomb-blockade phenomena at room temperature. The I=V staircases may be attributed to charging of As islands with sizes in the nanometer region, formed by As atoms from the top silicon layer of SOI wafer during ion implantation. These results open a new path to build a SiNWs by minimizing the diameter below 50 nm.
參考文獻
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