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  • 學位論文

以原子層沉積(ALD)製備不同比例及堆疊方式之氧化鉿鋯(HfZrO2)薄膜分析

Characterization of HfZrO2 High-k Dielectrics Stacked by Atomic Layer Deposition for Metal Gate MIS Applications

指導教授 : 劉傳璽 阮弼群
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摘要


隨著科技不斷演進,人們對於各種產品功能需求和要求都越來越高,由於SiO2的漏電流和可靠性問題已經接近其物理極限。為了解決這些問題,本研究則採用其中精度最高的薄膜沈積方式,有就是原子層沈積法(Atomic Layer Deposition,ALD) 作為本次的研究主要的製程,並透過不同製程參數以及堆疊方式探討其中的漏電流、活化能、普爾-法蘭克定律。我們運用ALD製程來製作不同沈積比例的HfZrO2薄膜,其主要ALD原子層沈積技術,實驗方式分別為,2循環、4循環、6循環,製備Hf:Zr 1:3、1:1、3:1共96循環的三種比例HZO薄膜,並用濺鍍的方式,沈積Al閘極,厚度為200奈米。使用RTA退火600℃ 持續30秒,我們會藉由改變試片的工作溫度來量測漏電流,並探討不同比例的ALD沈積方式對於電流傳導機制之影響。 本研究利用 Al/HfO2/p-Si MIS結構給一定電壓使元件產生漏電流反應的量測方式,取得其電流與電壓之關係,而後利用在不同溫度條件下,根據阿瑞尼斯方程式,經自然對數轉換後,取Ln(J)對溫度倒數(1/T)做圖,取其斜率萃取出活化能 Ea 值,並去分析比較循環數對於活化能 Ea值的影響。 關鍵字:薄膜、熱活化能、氧化鉿鋯、氧化層、傳導機制

並列摘要


In this study, we utilized atomic layer deposition (ALD) technique to form high-k dielectrics for MIS applications. Through different deposition ratios of HfO2 and ZrO2 high-k materials and the reaction cycles of ALD, the thermal activation energy of the leakage current and current conduction mechanism have been analyzed. The results reveal that the ALD reaction cycle has a significant impact on the thermal activation energy. In addition, this study analyzed the influence of the deposition ratio through the Poole-Frenkel conduction mechanism. The results show that the deposition ratio of 1:1 is the best, which can prevent electrons from stimulating the electrons through the film and causing leakage current due to the heating up. It has a dynamic dielectric constant of about 8-11, the energy barrier height is as high as 0.95 eV, and the activation energy is 0.64 eV. Compared with other deposition ratios and ALD reaction cycles, it exhibits the best characteristics. To conclude, through this study the films with the deposition ratio of 1:1the fewer defects, greater thermal activation energy, higher barrier height, and1 have greater dielectric constant. KEYWORD: Thin Films; Thermal Activation Energy; Conduction Mechanism.

參考文獻


參考文獻
[1] 劉傳璽,陳進來,第三版,半導體物理元件與製程-理論與實務,五南文 化出版社,2006。
[2] Momose, H. S., Ono, M., Yoshitomi, T., Ohguro, T., Nakamura, S. I., Saito, M., & Iwai, H. (1996). 1.5 nm direct-tunneling gate oxide si mosfet's. IEEE Transactions on Electron Devices, 43(8), 1233-1242.
[3] Robertson, J., & Peacock, P. W. (2003). Electronic structure and band offsets of high-dielectric-constant gate oxides. In High-κ Gate Dielectrics (pp. 372-396).
[4] Dennard, R. H., Gaensslen, F. H., Yu, H. N., Rideout, V. L., Bassous, E., & LeBlanc, A. R. (1974). Design of ion-implanted MOSFET's with very small physical dimensions. IEEE Journal of Solid-State Circuits, 9(5), 256-268.

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