- 學位論文
閘極基底觸發及基底接觸點調變之靜電防護N型金氧半場效電晶體元件電路
ESD NMOS Devices and Circuits of Substrate Gate Triggering and Substrate pickup Adjustment
摘要
本文針對金氧半場效電晶體(MOSFETs)不均勻電流分佈及基底或井接觸點（Substrate/Well Pick-Up）的短路（Butting）與置入（Inserted）方式議題做詳細研究，在0.18微米製程中，這兩項議題都會嚴重影響到ESD能力，因此在佈局基底接觸點部份做改善，佈局設計除了掛載外接電阻也在源極端埋藏P+接觸點塊，調變保護環(Guard Ring)與汲源極擴散區的距離或者無保護環佈局，以增加基底電阻值，促使內部寄生BJT開啟。基底接點的調變對於接觸點短路置入問題確實是有助益。另外，針對不均勻分佈為了降低觸發電壓(Vt1)以有效的改善提升第二次崩潰點，提出電阻電容基底閘極觸發(RC substrate-gate triggering)和電阻電容反相器之基底和閘極共同觸發(RC-inverter-substrate-gate triggering)N型金氧半場效電晶體方式來克服上述的問題，本文也搭配電阻電容閘極耦合與電阻電容基底觸發方式來做比較。電阻電容閘極耦合能降低觸發電壓(Vt1)，卻有閘極過壓的問題，所以使用了電阻電容基底和閘極觸發與掛載電阻電容反相器的方式來提升二次崩潰點電流與克服閘極過壓的問題。
並列摘要
This thesis studies ESD NMOSFET non-uniform current distribution and butting/inserted substrate/well pickup issues in detail. In 0.18um process, the both issues influence ESD capability seriously. Hence, improvement to substrate pickup layout has been design. In addition to extrinsic resistance connecting to the substrate, we also designed buried P+ pickups in the source, modulation of the spacing from drain/source to the guard ring distance to increase effecting substrate resistance values or without guard ring and enable turning on of the internal parasitic BJT. Substrate pickup adjustments improve the ESD robustness for indeed. Besides, aiming at improvement of non-uniform current distribution to reduce the trigger voltage (Vt1) and enhanc the second breakdown current, An RC-substrate-gate-triggering and RC-inverter-substrate-gate triggering NMOS style is proposed to solve the above issue. This thesis also uses RC-gate-coupled and RC-substrate-triggering NMOS style for comparison. Although the RC gate-coupled style can reduce trigger voltage, it could result in gate over-driving effect. Therefore, RC substrate-gate-triggering style with/without the inverter is utilized to raise second breakdown current and overcome the gate over-driving problem.