最簡定址架構類化型小腦模型控制器之學習收斂性分析

本文主要目的在證明最簡定址架構類化型小腦模型控制器(Simple addressing structure for Cerebellar Model Articulation Controller with General Basis Function ,S_CMAC_GBF)的收斂性。並證明其結果會以最小平方誤差收斂，同時應用S_CMAC_GBF硬體架構[14]、學習方式，進一步以FPGA硬體實現。原始小腦模型控制器有記憶體用量過多且無法應用於輸入高維度的問題，本文不但改良原始小腦膜控制器之缺點，且保有CMAC原本優異的非線性函數的學習能力與高精確度，也解決了傳統小腦模型控制器無法提供輸出對輸入的微分資訊與記憶體數目會隨著輸入變數的增加而成指數成長的問題，更進一步證明S_CMAC_GBF會以最小平方誤差收斂。根據S_CMAC_GBF架構以現場可規劃邏輯閘陣列(Field Programmable Gate Array, FPGA)晶片實現其硬體，如此不但擺脫電腦體積大與運算緩慢的缺點，且處理速度由 sec晉升到 sec更易於即時系統(real time)與線上學習(on-line)，在與其他晶片元件的搭配組合上也更方便。對於硬體之驗證，以兩個例子為之，一為微分-延遲的混沌系統，另一為複雜的非線性函數，將硬體FPGA之輸出與電腦軟體運算模擬結果比較得到相同優異之成效。

關鍵字

最簡定址架構類化型小腦模型控制；最小平方誤差；硬體實現；現場可規劃邏輯閘陣列

並列摘要

This paper is to prove the learning convergence of Simple addressing structure for Cerebellar Model Articulation Controller with General Basis Function, S_CMAC_GBF. The study result demonstrates the convergence to be Least Square Error. The S_CMAC_GBF hardware structure and learning method is proposed to be realized by FPGA hardware. Memory space over consumption and not able to be used in high dimensional input space systems are two disadvantages of original CMAC. In this study, these weak points are improved without losing the excellent nonlinear functional learning ability and high accuracy of original CMAC, also the traditional CMAC problem of unable providing output-to-input differentiability and memory space exponentially consumption alone with the increasing of input variables are solved in this study. Furthermore, it is proved that the convergence of S_CMAC_GBF is performed in Least Square Error to the optimum status. The hardware of S_CMAC_GBF structure is realized by a chip of Field Programmable Gate Array, FPGA, this can improve the disadvantages of computer big bulk and slow operation, the processing speed can be increased from sec to sec in real time system and on-line learning, it is also more convenient in the combinational match with other elements. Two examples are illustrated to demonstrate the hardware verification: Mackey-Glass Time Series and complex nonlinear function, the FPGA output and simulation result are analyzed and compared in the verification.