本論文第一部分研究以利用液相沉積法加退火製程成長良好的絕緣層在氮化鎵上,實驗先使用液相沉積法在低溫(<50℃)將二氧化矽沉積在氮化鎵/藍寶石基板上,將金屬電極以金/鈦或金/鉻為材料,蒸鍍在二氧化矽層上,接著退火400℃到900℃,藉金屬電極外加偏壓來作氧化層之漏電流量測分析比較。 第二部分研究超接面金氧半功率場效電晶體之電性模擬,了解具有高摻雜濃度的超級接面結構能夠有效改善崩潰電壓與導通電阻之間的關係。使用半導體元件模擬軟體為ISE TCAD,首先利用設計之元件結構來找出pn柱狀結構之最佳摻雜濃度、p型柱狀溝槽之最佳深度。再分析新設計元件結構對於崩潰電壓與導通電阻的影響。
In the first part of this paper, we try to grow a quality insulating film on the surface of GaN by the liquid phase deposition (LPD) and post annealing. After collecting and analyzing the leakage current of the insulator, we will find a suitable thickness of insulator and the annealing procedure. Secondary, we also study the high voltage semiconductor device – super junction metal oxide semiconductor field effect transistor (SJ MOSFET) by the simulation tools. In this thesis, a new structure of MOSFET is proposed. After the TCAD simulation, the on-resistance, breakdown voltage of the devices are collected under different geometry and doping concentration. From above data, we can find a good recipe and process window for the SJ MOSFET.