在0.18μm / 90nm CMOS製程中具有NMOS開關整合矽控整流器之雙極電晶體電路

SCR-Incorporated BJT Circuits with an NMOS Switch in 0.18μm / 90nm CMOS Process

黃義洲(Yi-Jou Huang)

指導教授 ： 黃至堯

健行科技大學/電資學院/電子工程所/碩士(2012年)

https://doi.org/10.6824/UCH.2012.00050

摘要

在0.18μm / 90nm CMOS製程裡，矽控整流器做為靜電防護用途因直流保持電壓表現過低，容易造成鎖定的現象而導致電路的故障，因此本創作發展一新型的電路結構從而改善保持電壓過低以致於鎖定的問題。以整合矽控整流器雙極電晶體元件的結構加入一N型金氧半電晶體或著電阻電容閘極耦合N型金氧半電晶體的架構，在此兩種電路中可將N型金氧半電晶體視為開關，當靜電打擊時N型金氧半電晶體能利用其導通特性來箝位並降低保持電壓，直流操作時N型金氧半電晶體關閉使得矽控整流器不易進入鎖定的狀態。具有N型金氧半電晶體的整合矽控整流器之雙極電晶體電路和具有RC閘極耦合N型金氧半電晶體的整合矽控整流器之雙極電晶體電路經直流、傳輸線脈波的量測結果，兩種架構的保持電壓都較傳統的矽控整流器提高了10倍以上，而且靜電強度也與矽控整流器相當。

關鍵字

靜電放電 ； 矽控整流器 ； 鎖定 ； 保持電壓

並列摘要

In 0.18μm / 90nm CMOS process, a traditional SCR used for ESD protection is easily susceptible into latch-up and leads to circuit failure due to very low DC holding voltage (VH) performance of the SCR. Therefore, this work develops new circuit structures in a 0.18μm CMOS process for further improving holding voltage and latch-up Immunity. This circuit integrates an SCR-incorporated BJT with either a single NMOS or RC-gate-coupled NMOS structure. During ESD zapping, the NMOS can be regarded as a switch in turn-on state to clamp ESD voltage and reduce the holding voltage to enable SCR action, while the NMOS is switched off to disable the SCR action during DC stand condition. The ESD threshold and holding voltage of this SCR-incorporated BJT with the above-mentioned structure has been verified by DC and TLP measurements. In consequence, the holding voltage of the both new structures is not only about sixteen-times higher than that of the traditional SCR, and the ESD robustness is also nearly the same as that the SCR.

並列關鍵字

electrostatic discharge (ESD) ； SCR ； latch-up ； holding voltage

參考文獻

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