靜電防護N型金氧半場效電晶體之短路與置入型接觸點改善設計與分析

ANALYSIS AND IMPROVEMENT OF INSERTED AND BUTTING SUBSTRATE PICKUP LAYOUT STYLE IN ESD NMOS DEVICES

宋柏寬(Po-Kuan Sung)

指導教授 ： 黃至堯

健行科技大學/電資學院/電子工程所/碩士(2008年)

https://doi.org/10.6824/UCH.2008.00032

摘要

多指狀Ｎ型靜電放電金氧半場效電晶體（multi-finger ESD NMOS）在0.18製程中，由於基底電阻短路的效應金氧半場效電晶體(MOSFETs)其基底或井接觸點（Substrate/Well Pick-Up）的短路（Butting）或置入（Inserted）接觸佈局會嚴重危害靜電強健度。因此，本文深入研究探討此佈局限制議題，外部電阻在NMOS基底本體與接地之間置入接觸可以大幅改善降低ESD傷害。基於這些考量，我們佈局上設計出八種類型的多指狀結構，藉以得到其相關參數特性趨勢，進而改善靜電放電效能。另外在元件模擬部分針對短路（butting）結構與閘極接地（gate-grounded）結構比較，分析結果顯示短路結構會造成較小的基底電阻，導致於內部寄生BJT不易導通，進而影響NMOS 元件強健度並降低了靜電放電效能。

關鍵字

基底電阻 ； 靜電放電 ； 短路接觸 ； 置入接觸 ； 接觸點

並列摘要

In multi-finger ESD NMOS, the butting or inserted layout of the substrate/well pickups of MOSFETs strictly degrades ESD robustness owing to the substrate resistance shorting effect. Therefore, this thesis studies on this layout restriction issue in detail. Extrinsic well/diffusion resistance insertion between the NMOS substrate body and ground can greatly improve the ESD performance degradation. Hence, we design eight types of the NMOS multi-finger layout plots, in order to obtain related mechanism parameters and hence improve ESD performance. In the simulation part, we focus on the butting/inserted NMOS structure, and comparing to the gate-grounded NMOS. The analysis results imply that butting/inserted substrate pickup leads to small substrate resistance, so that the parasitic NPN BJT can hardly turn on, and thus reduce the ESD robustness of the NMOS device.

並列關鍵字

substrate resistance ； electrostatic discharge (ESD) ； butting ； inserted ； pickup

參考文獻

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