近年來,新世代快閃記憶體因為半導體技術的進步,使得儲存單元越來越小,資料的干擾 和維持問題卻變得越來越嚴重,也因此降低了記憶體的可靠度。為了增加記憶體的可靠度,錯誤更 正碼被建議在記憶體的存取其間改正錯誤。目前已經有一些應用於記憶體的錯誤更正碼之設計被提 出,BCH和RS碼是其中最有效的兩種代數碼而且也已經被廣泛得應用,而近年來low-density parity-check (LDPC)碼也已經被提出應用於先進的通訊系統。在本篇論文中,我們著重於在所有位 元所發生錯誤的機率皆為獨立發生的前提下,設計EG-LDPC(65535, 58975, t=257)的編碼器以及解 碼器。在我們的系統中使用了各種先進的架構,為了要降低系統的時脈週期個數,我們將平行的架構應用於encoder區塊和decoder區塊。而對於LDPC碼解碼的演算法,我們則是使用了Majority-logic decoding algorithm。最後以Xilinx FPGA確認及模擬編碼器/解碼器的架構。解碼器的最大頻率為51.6MHz而全部所需的gate count為1512.7K.
Recently, flash memories with reduced cell sizes are popular in applications such that issues like disturbs and data retention become critical. Hence, the reliability of memories has decreased. In order to increase the reliability of memories, error-control coding has been suggested to correct errors during memory reading. There are already some researches of the hardware design of error correcting codes in storage equipments. BCH and RS codes are the most powerful known algebraic codes and are widely used. In very recent years, low-density parity-check (LDPC) have been proposed to be implemented advanced communication systems. In this thesis, we focus on the encoder/decoder design of EG-LDPC (65535; 58975; 257) codes for flash memory under the condition that the error probability of all bits are independent. We propose various advanced architectures in our system. The parallel architecture is used to encoder block and decoding block in order to reduce system's clock cycles. Majority-logic decoding algorithm is chosen to decode the LDPC code. Finally, the encoder/decoder architecture is confirmed and simulated by Xilinx FPGA. The FPGA device we used is Virtex6 XC6VHX565T, the package is FF1923, and the speed grade is -2. The maximum frequency and total equivalent gate count for the decoder are 51.6MHz and 1512.7K.