低功率低失真4階2-2串接三角積分調變器設計

Design of a Low-Power Low-Distortion Fourth Order 2-2 Cascaded Delta-Sigma Modulator

陸奕成(I-Cheng Lu)

指導教授 ： 劉萬榮

共同指導教授 ： 林嘉洤

國立臺北大學/電機資訊學院/電機工程研究所/碩士(2013年)

摘要

本論文將探討與設計一個應用於音頻範圍的高解析度超取樣率Delta-Sigma類比數位轉換器，並使用低失真疊接三角積分器架構搭配低功率交換式電容積分器，來達到低功率、低面積、低失真的設計要求。本論文採用TSMC 0.18微米標準製程進行設計，並且以MATLAB先對系統行為模式進行模擬與規格評估，再使用Hspice對電路特性進行模擬與實踐。整體電路操作於20kHz的頻寬，取樣頻率為2.56MHz，以及1.8V的供應電壓，最大SNDR值為64.8dB，功率消耗為1.2mW，總佈局面積為1.027 x0.833 mm2。

關鍵字

三角積分調變器 ； 低失真 ； 低功率交換式電容積分器

並列摘要

The thesis will discuss and design a high resolution Delta-Sigma analog-to-digital converter that applied to the audio frequency range and use the low-distortion delta-sigma topologies for MASH architectures employing low-power switched capacitor integrator to achieve the requirements of a low-power, low-area, and low-distortion design. This modulator was integrated in TSMC 0.18um CMOS technologies. Overall circuit operation is of 20kHz bandwidth, sampling frequency of 2.56MHz, and 1.8V supply voltage. The maximum SNDR is 64.8dB, total power dissipation is 1.2mW, and the layout area is 1.027 x0.833 mm2.

並列關鍵字

delta-sigma modulator ； low-distortion ； low-power switched capacitor integrator

參考文獻

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