高速平行處理循環冗餘校驗電路的實現

Implementation of High-Speed Parallel CRC Circuits

盧銘佑(Ming-Yu Lu)

指導教授 ： 謝欣霖

共同指導教授 ： 韓永祥(Yunghsiang S. Han)

國立臺北大學/電機資訊學院/通訊工程研究所/碩士(2012年)

摘要

在目前現代化的科技之下，資料的傳輸也越來越快，傳輸上的錯誤也會一直不斷的發生。錯誤控制編碼(Error control Coding)，在對於處理資料傳輸上的錯誤是一種非常有用的方法，並且被廣泛的使用在資料通訊傳輸上及儲存系統上。錯誤控制碼可以確保我們在接收資料的正確性。
本篇論文運用了平行處理實現了循環冗餘校驗(CRC)輸入與輸出的電路。有效運用CRC電路設計的平行處理一次輸入位元,就可以完成串列傳輸CRC的電路。該電路實現了平行處理輸入8位元的CRC-8-CCITT，CRC-16-CCITT，CRC-32-CCITT。另外也實現了輸入16位元和32位元的CRC-32-CCITT。此外也加入MIMA演算法與原來平行處理輸入16位元的CRC-32-CCITT做比較。所有電路都使用FPGA軟體來算出gate-count並且做比較。

關鍵字

錯誤控制編碼 ； 循環冗餘校驗

並列摘要

In modern technology using fast data transmission, transmission errors frequently occur. Error control coding is very useful to combat errors and widely used in the transmission of data communication and storage systems. Error control coding can ensure that the correct information will be received.
This thesis deals with the implementation of cyclic redundancy check (CRC) circuits with parallel inputs and outputs. Area-efficient CRC circuits are designed such that parallel inputs can be fed into the circuit to perform CRC for the information sequence. The circuits are implemented for the CRC-8-CCITT, CRC-16-CCITT, and CRC-32-CCITT with parallel 8-bit inputs. Furthermore, the CRC-32 are implemented with 16-bit and 32-bit input. In addition, the MIMA algorithm is proposed to compare with the original 16-bit CRC32-CCITT design. All circuits are tested by FPGA software and gate-count for them are compared.

並列關鍵字

Error control Coding ； CRC

參考文獻

[1] S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Prentice-Hall, 2004.

[3] A. Patel, “A multichannel crc register,” in Proc. AFIPS Conf, Ed., vol. 38, Feb. 1971,pp. 11–14.

[4] T. B. Pei and C. Zukowski, “High-speed parallel CRC circuits in VLSI,” IEEE Trans. Commun., vol. 40, no

4, pp. 653–657, Apr. 1992.

[5] Y. Chen and K. K. Parhi, “Small area parallel Chien search architectures for long BCH codes,” IEEE Trans. VLSI, vol. 12, no. 5, pp. 545–549, May 2004.