- 學位論文
鎖相迴路中具自動相位偵測選擇器之內建抖動訊號量測電路
On Chip Jitter Signal Measurement Circuit With Automatic Phase Deteting Selector In PLL
摘要
鎖相迴路它是一個數位與類比的混合頻率處理電路，混合頻率電路在整個系統晶片(System On Chip)中是較難以測試的，故在設計混合頻率電路時，需要留意電路本身性能之外，仍需要考量晶片完成後之測試考量，且加入不影響電路本身工作特性的額外電路，使電路晶片化時，成為一個具有量測其本身電路的特性與功能，具有晶片可測性的功能，以降低量測時間與測試成本。 本論文所要探討的是鎖相迴路中具自動相位偵測選擇器之內建抖動訊號量測電路，其內建週期時脈抖動量測電路可以自動判斷鎖相迴路輸出訊號與輸入的參考訊號之間的相位領先與落後的問題，再藉由時間數位轉換器輸出數位二進制碼，來得知鎖相迴路的時脈抖動之數值，繼而得到統計值，進而分析以得知之統計值去換算求得時脈均方根值，而完成週期時脈抖動的變動量之量測。 論文中的鎖相迴路和週期抖動訊號量測電路皆採取TSMC 0.35um 2p4m之全客戶式設計流程實現與模擬設計。
並列摘要
Phase locked loops (PLL) are the mixed-mode circuits which process analog and digital circuits. Mixed-mode circuits are difficult to be measured actually for a system-on-chip (SOC) chip. Hence, it is indispensable to consider the measurement techniques for fabricated chips except for performances of designed circuits. This is usually fulfilled by integrating extra circuits on the chip to make designed chips self-testable. With the architecture, the measurement time and cost can be reduced. In this thesis, we study the self-testable jitter measurement circuit for PLL in which an automatic phase detector is included to judge the phase relationship between the reference signal and the output of PLL and then switch the both signals to the correct input terminals of the time-to-digit converter. This will make the phase difference between the both signals become a binary code which indicates the jitter of the fabricated PLL. The period jitter can be obtained by the root-mean-square calculation of these statistical measurement values. In this thesis, the circuits are designed and fabricated under the TSMC 0.35um 2p4m processes.